Method for reducing or eliminating interface defects in mismatched semiconductor epilayers
Abstract
The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10[times] critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In[sub 0.05]Ga[sub 0.95]As/(001)GaAs interface was controlled by fabricating 2-[mu]m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500 [angstrom] of In[sub 0.05]Ga[sub 0.95]As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-[mu]m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 [mu]m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density. 7 figs.
- Inventors:
- Issue Date:
- OSTI Identifier:
- 7233458
- Patent Number(s):
- 5156995
- Application Number:
- PPN: US 7-684128
- Assignee:
- Cornell Research Foundation, Inc., Ithaca, NY (United States)
- DOE Contract Number:
- FG02-86ER45278
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 12 Apr 1991
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 36 MATERIALS SCIENCE; GALLIUM ARSENIDES; FABRICATION; INTERFACES; INDIUM ARSENIDES; DISLOCATIONS; COMPOSITE MATERIALS; SEMICONDUCTOR MATERIALS; ARSENIC COMPOUNDS; ARSENIDES; CRYSTAL DEFECTS; CRYSTAL STRUCTURE; GALLIUM COMPOUNDS; INDIUM COMPOUNDS; LINE DEFECTS; MATERIALS; PNICTIDES; 360601* - Other Materials- Preparation & Manufacture; 360602 - Other Materials- Structure & Phase Studies
Citation Formats
Fitzgerald, Jr, E A, and Ast, D G. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers. United States: N. p., 1992.
Web.
Fitzgerald, Jr, E A, & Ast, D G. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers. United States.
Fitzgerald, Jr, E A, and Ast, D G. Tue .
"Method for reducing or eliminating interface defects in mismatched semiconductor epilayers". United States.
@article{osti_7233458,
title = {Method for reducing or eliminating interface defects in mismatched semiconductor epilayers},
author = {Fitzgerald, Jr, E A and Ast, D G},
abstractNote = {The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10[times] critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In[sub 0.05]Ga[sub 0.95]As/(001)GaAs interface was controlled by fabricating 2-[mu]m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500 [angstrom] of In[sub 0.05]Ga[sub 0.95]As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-[mu]m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 [mu]m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density. 7 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1992},
month = {10}
}