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Title: Parallel pulse processing and data acquisition for high speed, low error flow cytometry

Abstract

A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all channels. After an event has been stored in each FIFO, a bus controller moves the oldest entry from each FIFO buffer onto a common data bus. The trigger circuit generates an ID number for each FIFO entry, which is checked by an error detection circuit. The system has high speed and low error rate. 17 figs.

Inventors:
;
Issue Date:
OSTI Identifier:
7117193
Patent Number(s):
5150313 A
Application Number:
PPN: US 7-508226
Assignee:
Univ. of California, Oakland, CA (United States) PTO; EDB-94-091144
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Resource Relation:
Patent File Date: 12 Apr 1990
Country of Publication:
United States
Language:
English
Subject:
59 BASIC BIOLOGICAL SCIENCES; CELL FLOW SYSTEMS; DESIGN; ANIMAL CELLS; CYTOLOGICAL TECHNIQUES; CYTOLOGY; BIOLOGY; 550300* - Cytology

Citation Formats

Engh, G.J. van den, and Stokdijk, W. Parallel pulse processing and data acquisition for high speed, low error flow cytometry. United States: N. p., 1992. Web.
Engh, G.J. van den, & Stokdijk, W. Parallel pulse processing and data acquisition for high speed, low error flow cytometry. United States.
Engh, G.J. van den, and Stokdijk, W. Tue . "Parallel pulse processing and data acquisition for high speed, low error flow cytometry". United States.
@article{osti_7117193,
title = {Parallel pulse processing and data acquisition for high speed, low error flow cytometry},
author = {Engh, G.J. van den and Stokdijk, W.},
abstractNote = {A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all channels. After an event has been stored in each FIFO, a bus controller moves the oldest entry from each FIFO buffer onto a common data bus. The trigger circuit generates an ID number for each FIFO entry, which is checked by an error detection circuit. The system has high speed and low error rate. 17 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1992},
month = {9}
}