A random access memory immune to single event upset using a T-Resistor

Ochoa, A Jr

Title: A random access memory immune to single event upset using a T-Resistor

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Abstract

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Inventors:: Ochoa, A Jr

Issue Date:: 1987-10-28

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

OSTI Identifier:: 6852794

Patent Number(s):: 6113695

Assignee:: SNL; EDB-88-182128

Patent Classifications (CPCs):: B - PERFORMING OPERATIONS B05 - SPRAYING OR ATOMISING IN GENERAL B05C - APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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B - PERFORMING OPERATIONS B05 - SPRAYING OR ATOMISING IN GENERAL B05C - APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
B05C11/08 - Spreading liquid or other fluent material by manipulating the work, e.g. tilting

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L21/6715 - {Apparatus for applying a liquid, a resin, an ink or the like

B - PERFORMING OPERATIONS B05 - SPRAYING OR ATOMISING IN GENERAL B05C - APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
B05C11/1047 - {Apparatus or installations for supplying liquid or other fluent material comprising a buffer container or an accumulator between the supply source and the applicator}

F - MECHANICAL ENGINEERING F16 - ENGINEERING ELEMENTS AND UNITS F16K - VALVES
F16K31/004 - {actuated by piezo-electric means}

B - PERFORMING OPERATIONS B05 - SPRAYING OR ATOMISING IN GENERAL B05C - APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
B05C11/1026 - {Valves

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DOE Contract Number:: AC04-76DP00789

Resource Type:: Patent

Resource Relation:: Other Information: Portions of this document are illegible in microfiche products

Country of Publication:: United States

Language:: English

Subject:: 99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; 42 ENGINEERING; MEMORY DEVICES; DESIGN; INVENTIONS; MOS TRANSISTORS; MOSFET; SEMICONDUCTOR MATERIALS; FIELD EFFECT TRANSISTORS; MATERIALS; SEMICONDUCTOR DEVICES; TRANSISTORS; 990220* - Computers, Computerized Models, & Computer Programs- (1987-1989); 420800 - Engineering- Electronic Circuits & Devices- (-1989)

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                    Ochoa, A Jr. A random access memory immune to single event upset using a T-Resistor.  United States: N. p., 1987. 
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                    Ochoa, A Jr. A random access memory immune to single event upset using a T-Resistor.  United States.

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                    Ochoa, A Jr. Wed .  
        "A random access memory immune to single event upset using a T-Resistor".  United States.

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@article{osti_6852794,

  title        = {A random access memory immune to single event upset using a T-Resistor},

  author       = {Ochoa, A Jr},

  abstractNote = {In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {1987},

  month        = {10}

}

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