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Title: A random access memory immune to single event upset using a T-Resistor

Abstract

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Inventors:
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
OSTI Identifier:
6852794
Patent Number(s):
6113695
Assignee:
SNL; EDB-88-182128
Patent Classifications (CPCs):
B - PERFORMING OPERATIONS B05 - SPRAYING OR ATOMISING IN GENERAL B05C - APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Resource Relation:
Other Information: Portions of this document are illegible in microfiche products
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; 42 ENGINEERING; MEMORY DEVICES; DESIGN; INVENTIONS; MOS TRANSISTORS; MOSFET; SEMICONDUCTOR MATERIALS; FIELD EFFECT TRANSISTORS; MATERIALS; SEMICONDUCTOR DEVICES; TRANSISTORS; 990220* - Computers, Computerized Models, & Computer Programs- (1987-1989); 420800 - Engineering- Electronic Circuits & Devices- (-1989)

Citation Formats

Ochoa, A Jr. A random access memory immune to single event upset using a T-Resistor. United States: N. p., 1987. Web.
Ochoa, A Jr. A random access memory immune to single event upset using a T-Resistor. United States.
Ochoa, A Jr. Wed . "A random access memory immune to single event upset using a T-Resistor". United States.
@article{osti_6852794,
title = {A random access memory immune to single event upset using a T-Resistor},
author = {Ochoa, A Jr},
abstractNote = {In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1987},
month = {10}
}