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Title: Process for 3D chip stacking

Abstract

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Inventors:
Issue Date:
Research Org.:
Univ. of California (United States)
Sponsoring Org.:
USDOE, Washington, DC (United States)
OSTI Identifier:
675842
Patent Number(s):
5834162
Application Number:
PAN: 8-739,082
Assignee:
Univ. of California, Oakland, CA (United States)
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Resource Relation:
Other Information: PBD: 10 Nov 1998
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; FABRICATION; ELECTRIC CONTACTS; INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; LASER RADIATION; PERFORMANCE

Citation Formats

Malba, V. Process for 3D chip stacking. United States: N. p., 1998. Web.
Malba, V. Process for 3D chip stacking. United States.
Malba, V. Tue . "Process for 3D chip stacking". United States.
@article{osti_675842,
title = {Process for 3D chip stacking},
author = {Malba, V},
abstractNote = {A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1998},
month = {11}
}