High density electronic circuit and process for making
Abstract
High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.
- Inventors:
- Issue Date:
- Sponsoring Org.:
- USDOE; USDOE, Washington, DC (United States)
- OSTI Identifier:
- 6325790
- Patent Number(s):
- 5918153
- Application Number:
- PPN: US 8-715659
- Assignee:
- Sandia Corp., Albuquerque, NM (United States)
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 18 Sep 1996
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING; DESIGN; ELECTRONIC CIRCUITS; FABRICATION; SUBSTRATES; TESTING; 426000* - Engineering- Components, Electron Devices & Circuits- (1990-)
Citation Formats
Morgan, W P. High density electronic circuit and process for making. United States: N. p., 1999.
Web.
Morgan, W P. High density electronic circuit and process for making. United States.
Morgan, W P. Tue .
"High density electronic circuit and process for making". United States.
@article{osti_6325790,
title = {High density electronic circuit and process for making},
author = {Morgan, W P},
abstractNote = {High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1999},
month = {6}
}
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