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Title: Interconnection networks

Abstract

A network of interconnected processors is formed from a vertex symmetric graph selected from graphs GAMMA/sub d/(k) with degree d, diameter k, and (d + 1)exclamation/ (d /minus/ k + 1)exclamation processors for each d greater than or equal to k and GAMMA/sub d/(k, /minus/1) with degree d /minus/ 1, diameter k + 1, and (d + 1)exclamation/(d /minus/ k + 1)exclamation processors for each d greater than or equal to k greater than or equal to 4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network GAMMA/sub d/(k, /minus/1) is provided, no processor has a channel connected to form an edge in a direction delta/sub 1/. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address tomore » a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations. 9 figs.« less

Inventors:
;
Issue Date:
Research Org.:
Los Alamos National Lab., NM (USA)
OSTI Identifier:
6316175
Patent Number(s):
-US-A7209238
Application Number:
ON: DE89010965
Assignee:
Dept. of Energy TIC; ERA-14-027775; EDB-89-075573
DOE Contract Number:  
W-7405-ENG-36
Resource Type:
Patent
Resource Relation:
Other Information: Paper copy only, copy does not permit microfiche production
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; COMPUTER NETWORKS; PARALLEL PROCESSING; ALGORITHMS; ARRAY PROCESSORS; COMPUTER ARCHITECTURE; DATA TRANSMISSION; GRAPHS; INVENTIONS; MEMORY DEVICES; NUMERICAL ANALYSIS; ROUTING; VERTEX FUNCTIONS; COMMUNICATIONS; FUNCTIONS; MATHEMATICAL LOGIC; MATHEMATICS; PROGRAMMING; 990220* - Computers, Computerized Models, & Computer Programs- (1987-1989)

Citation Formats

Faber, V., and Moore, J.W. Interconnection networks. United States: N. p., 1988. Web.
Faber, V., & Moore, J.W. Interconnection networks. United States.
Faber, V., and Moore, J.W. Mon . "Interconnection networks". United States.
@article{osti_6316175,
title = {Interconnection networks},
author = {Faber, V. and Moore, J.W.},
abstractNote = {A network of interconnected processors is formed from a vertex symmetric graph selected from graphs GAMMA/sub d/(k) with degree d, diameter k, and (d + 1)exclamation/ (d /minus/ k + 1)exclamation processors for each d greater than or equal to k and GAMMA/sub d/(k, /minus/1) with degree d /minus/ 1, diameter k + 1, and (d + 1)exclamation/(d /minus/ k + 1)exclamation processors for each d greater than or equal to k greater than or equal to 4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network GAMMA/sub d/(k, /minus/1) is provided, no processor has a channel connected to form an edge in a direction delta/sub 1/. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations. 9 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1988},
month = {6}
}