DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Planarization of metal films for multilevel interconnects

Abstract

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Inventors:
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
OSTI Identifier:
5656740
Application Number:
ON: DE86013743
Assignee:
Dept. of Energy
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Resource Relation:
Other Information: Portions of this document are illegible in microfiche products
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; INTEGRATED CIRCUITS; FABRICATION; LASER WELDING; ELECTRONIC CIRCUITS; JOINING; MICROELECTRONIC CIRCUITS; WELDING; 420800* - Engineering- Electronic Circuits & Devices- (-1989)

Citation Formats

Tuckerman, D B. Planarization of metal films for multilevel interconnects. United States: N. p., 1985. Web.
Tuckerman, D B. Planarization of metal films for multilevel interconnects. United States.
Tuckerman, D B. Mon . "Planarization of metal films for multilevel interconnects". United States.
@article{osti_5656740,
title = {Planarization of metal films for multilevel interconnects},
author = {Tuckerman, D B},
abstractNote = {In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Mon Jun 24 00:00:00 EDT 1985},
month = {Mon Jun 24 00:00:00 EDT 1985}
}

Patent:
Search for the full text at the U.S. Patent and Trademark Office Note: You will be redirected to the USPTO site, which may require a pop-up blocker to be deactivated to view the patent. If so, you will need to manually turn off your browser's pop-up blocker, typically found within the browser settings. (See DOE Patents FAQs for more information.)

Save / Share: