Global to push GA events into
skip to main content

Title: Electrochemical planarization

In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer. 12 figures.
Inventors:
;
Issue Date:
OSTI Identifier:
5354406
Assignee:
Dept. of Energy, Washington, DC (United States) PTO; EDB-94-046709
Patent Number(s):
US 5256565; A
Application Number:
PPN: US 7-348982
Contract Number:
W-7405-ENG-48
Resource Relation:
Patent File Date: 8 May 1989
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; INTEGRATED CIRCUITS; FABRICATION; ELECTROPOLISHING; ETCHING; METALS; THIN FILMS; ELECTROLYSIS; ELECTRONIC CIRCUITS; ELEMENTS; FILMS; LYSIS; MICROELECTRONIC CIRCUITS; POLISHING; SURFACE FINISHING; 426000* - Engineering- Components, Electron Devices & Circuits- (1990-)