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Title: Direct match data flow machine apparatus and process for data driven computing

Abstract

A data flow computer and method of computing are disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the correspondingmore » data parameter is to be reused. The tag memory outputs a ``fire`` signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.« less

Inventors:
;
Issue Date:
Research Org.:
AT&T Corporation
Sponsoring Org.:
USDOE, Washington, DC (United States)
OSTI Identifier:
527751
Patent Number(s):
5,657,465
Application Number:
PAN: 8-403,603
Assignee:
Sandia Corp., Albuquerque, NM (United States) SNL; SCA: 990200; PA: EDB-97:128894; SN: 97001843795
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Resource Relation:
Other Information: PBD: 12 Aug 1997
Country of Publication:
United States
Language:
English
Subject:
99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; COMPUTERS; DATA-FLOW PROCESSING; COMPUTER ARCHITECTURE; MEMORY MANAGEMENT; DATA TRANSMISSION

Citation Formats

Davidson, G.S., and Grafe, V.G. Direct match data flow machine apparatus and process for data driven computing. United States: N. p., 1997. Web.
Davidson, G.S., & Grafe, V.G. Direct match data flow machine apparatus and process for data driven computing. United States.
Davidson, G.S., and Grafe, V.G. Tue . "Direct match data flow machine apparatus and process for data driven computing". United States.
@article{osti_527751,
title = {Direct match data flow machine apparatus and process for data driven computing},
author = {Davidson, G.S. and Grafe, V.G.},
abstractNote = {A data flow computer and method of computing are disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ``fire`` signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1997},
month = {8}
}