Repairable chip bonding/interconnect process
Abstract
A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.
- Inventors:
- Issue Date:
- Research Org.:
- Univ. of California (United States)
- Sponsoring Org.:
- USDOE, Washington, DC (United States)
- OSTI Identifier:
- 516937
- Patent Number(s):
- 5653019
- Application Number:
- PAN: 8-522,471
- Assignee:
- Univ. of California, Oakland, CA (United States)
- DOE Contract Number:
- W-7405-ENG-48
- Resource Type:
- Patent
- Resource Relation:
- Other Information: PBD: 5 Aug 1997
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; INTEGRATED CIRCUITS; FABRICATION; REPAIR; LASERS; SOLDERING; TESTING
Citation Formats
Bernhardt, A F, Contolini, R J, Malba, V, and Riddle, R A. Repairable chip bonding/interconnect process. United States: N. p., 1997.
Web.
Bernhardt, A F, Contolini, R J, Malba, V, & Riddle, R A. Repairable chip bonding/interconnect process. United States.
Bernhardt, A F, Contolini, R J, Malba, V, and Riddle, R A. Tue .
"Repairable chip bonding/interconnect process". United States.
@article{osti_516937,
title = {Repairable chip bonding/interconnect process},
author = {Bernhardt, A F and Contolini, R J and Malba, V and Riddle, R A},
abstractNote = {A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Aug 05 00:00:00 EDT 1997},
month = {Tue Aug 05 00:00:00 EDT 1997}
}
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