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Title: On-clip high frequency reliability and failure test structures

Abstract

Self-stressing test structures for realistic high frequency reliability characterizations. An on-chip high frequency oscillator, controlled by DC signals from off-chip, provides a range of high frequency pulses to test structures. The test structures provide information with regard to a variety of reliability failure mechanisms, including hot-carriers, electromigration, and oxide breakdown. The system is normally integrated at the wafer level to predict the failure mechanisms of the production integrated circuits on the same wafer. 22 figs.

Inventors:
;
Issue Date:
Research Org.:
AT&T Corporation
OSTI Identifier:
504963
Patent Number(s):
5,625,288
Application Number:
PAN: 8-590,690
Assignee:
Sandia Corp., Albuquerque, NM (United States)
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Resource Relation:
Other Information: PBD: 29 Apr 1997
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; INTEGRATED CIRCUITS; RELIABILITY; PERFORMANCE TESTING; OSCILLATORS; FAILURES

Citation Formats

Snyder, E S, and Campbell, D V. On-clip high frequency reliability and failure test structures. United States: N. p., 1997. Web.
Snyder, E S, & Campbell, D V. On-clip high frequency reliability and failure test structures. United States.
Snyder, E S, and Campbell, D V. Tue . "On-clip high frequency reliability and failure test structures". United States.
@article{osti_504963,
title = {On-clip high frequency reliability and failure test structures},
author = {Snyder, E S and Campbell, D V},
abstractNote = {Self-stressing test structures for realistic high frequency reliability characterizations. An on-chip high frequency oscillator, controlled by DC signals from off-chip, provides a range of high frequency pulses to test structures. The test structures provide information with regard to a variety of reliability failure mechanisms, including hot-carriers, electromigration, and oxide breakdown. The system is normally integrated at the wafer level to predict the failure mechanisms of the production integrated circuits on the same wafer. 22 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1997},
month = {4}
}