skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: High performance static latches with complete single event upset immunity

Abstract

An asymmetric response latch providing immunity to single event upset without loss of speed is described. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states. 5 figures.

Inventors:
;
Issue Date:
OSTI Identifier:
5037725
Patent Number(s):
5307142 A
Application Number:
PPN: US 7-793084
Assignee:
Dept. of Energy, Washington, DC (United States) SNL; EDB-94-076790
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Resource Relation:
Patent File Date: 15 Nov 1991
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; ELECTRONIC EQUIPMENT; EQUIPMENT PROTECTION DEVICES; DESIGN; FAILURES; PERFORMANCE; EQUIPMENT; 426000* - Engineering- Components, Electron Devices & Circuits- (1990-)

Citation Formats

Corbett, W.T., and Weaver, H.T. High performance static latches with complete single event upset immunity. United States: N. p., 1994. Web.
Corbett, W.T., & Weaver, H.T. High performance static latches with complete single event upset immunity. United States.
Corbett, W.T., and Weaver, H.T. Tue . "High performance static latches with complete single event upset immunity". United States.
@article{osti_5037725,
title = {High performance static latches with complete single event upset immunity},
author = {Corbett, W.T. and Weaver, H.T.},
abstractNote = {An asymmetric response latch providing immunity to single event upset without loss of speed is described. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states. 5 figures.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1994},
month = {4}
}