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Title: Method for shallow junction formation

A doping sequence is disclosed that reduces the cost and complexity of forming source/drain regions in complementary metal oxide silicon (CMOS) integrated circuit technologies. The process combines the use of patterned excimer laser annealing, dopant-saturated spin-on glass, silicide contact structures and interference effects creates by thin dielectric layers to produce source and drain junctions that are ultrashallow in depth but exhibit low sheet and contact resistance. The process utilizes no photolithography and can be achieved without the use of expensive vacuum equipment. The process margins are wide, and yield loss due to contact of the ultrashallow dopants is eliminated. 8 figs.
Inventors:
Issue Date:
OSTI Identifier:
392651
Assignee:
Univ. of California, Oakland, CA (United States) PTO; SCA: 426000; PA: EDB-96:166877; SN: 96001682416
Patent Number(s):
US 5,569,624/A/
Application Number:
PAN: 8-464,021
Contract Number:
W-7405-ENG-48
Resource Relation:
Other Information: PBD: 29 Oct 1996
Research Org:
University of California
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; SEMICONDUCTOR JUNCTIONS; FABRICATION; INTEGRATED CIRCUITS; CRYSTAL DOPING; LASER RADIATION; DIELECTRIC MATERIALS