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Title: Elevated voltage level I{sub DDQ} failure testing of integrated circuits

Abstract

Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.

Inventors:
Issue Date:
Research Org.:
Sandia Corporation
OSTI Identifier:
238071
Patent Number(s):
5,519,333
Application Number:
PAN: 8-303,849
Assignee:
Sandia Corp., Albuquerque, NM (United States)
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Other Information: PBD: 21 May 1996
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; INTEGRATED CIRCUITS; TESTING; FAILURES; ELECTRIC POTENTIAL; OPERATION

Citation Formats

Righter, A W. Elevated voltage level I{sub DDQ} failure testing of integrated circuits. United States: N. p., 1996. Web.
Righter, A W. Elevated voltage level I{sub DDQ} failure testing of integrated circuits. United States.
Righter, A W. Tue . "Elevated voltage level I{sub DDQ} failure testing of integrated circuits". United States.
@article{osti_238071,
title = {Elevated voltage level I{sub DDQ} failure testing of integrated circuits},
author = {Righter, A W},
abstractNote = {Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1996},
month = {5}
}