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Title: Elevated voltage level I{sub DDQ} failure testing of integrated circuits

Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.
Inventors:
Issue Date:
OSTI Identifier:
238071
Assignee:
Sandia Corp., Albuquerque, NM (United States) SNL; SCA: 420500; PA: EDB-96:094722; SN: 96001594381
Patent Number(s):
US 5,519,333/A/
Application Number:
PAN: 8-303,849
Contract Number:
AC04-94AL85000
Resource Relation:
Other Information: PBD: 21 May 1996
Research Org:
Sandia Corporation
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; INTEGRATED CIRCUITS; TESTING; FAILURES; ELECTRIC POTENTIAL; OPERATION

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