SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions
Abstract
An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
- Inventors:
- Issue Date:
- Research Org.:
- US Dept. of Energy (USDOE), Washington, DC (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 2293946
- Patent Number(s):
- 11838021
- Application Number:
- 17/229,277
- Assignee:
- Barlow, Matthew, Springdale, AR (United States)
- DOE Contract Number:
- SC0017131
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 04/13/2021
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Barlow, Matthew, and Holmes, James A. SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions. United States: N. p., 2023.
Web.
Barlow, Matthew, & Holmes, James A. SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions. United States.
Barlow, Matthew, and Holmes, James A. Tue .
"SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions". United States. https://www.osti.gov/servlets/purl/2293946.
@article{osti_2293946,
title = {SiC jfet logic output level-shifting using integrated-series forward-biased jfet gate-to-channel diode junctions},
author = {Barlow, Matthew and Holmes, James A.},
abstractNote = {An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {12}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
N channel JFET based digital logic gate structure
patent, March 2010
- Krasowski, Michael J.
- US Patent Document 7,688,117
SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions
patent, March 2020
- Barlow, Matthew; Holmes, James A.
- US Patent Document 10,608,636
N channel JFET based digital logic gate structure
patent, April 2013
- Krasowski, Michael J.
- US Patent Document 8,416,007
JFET series connection
patent, June 2014
- Biela, Jürgen; Kolar, Johann; Aggeler, Daniel
- US Patent Document 8,760,214
Method for providing semiconductors having self-aligned ion implant
patent, May 2011
- Neudeck, Philip G.
- US Patent Document 7,935,601
Method for providing semiconductors having self-aligned ion implant
patent, September 2014
- Neudeck, Philip G.
- US Patent Document 8,841,698
High voltage switch module
patent, January 2018
- Zhang, Hao; Li, Xueqing; Bhalla, Anup
- US Patent Document 9,866,213