Techniques for storing data to enhance recovery and detection of data corruption errors
Abstract
Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 2293731
- Patent Number(s):
- 11789811
- Application Number:
- 17/746,627
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620719
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 05/17/2022
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Mills, Peter, Sullivan, Michael, Saxena, Nirmal, and Brooks, John. Techniques for storing data to enhance recovery and detection of data corruption errors. United States: N. p., 2023.
Web.
Mills, Peter, Sullivan, Michael, Saxena, Nirmal, & Brooks, John. Techniques for storing data to enhance recovery and detection of data corruption errors. United States.
Mills, Peter, Sullivan, Michael, Saxena, Nirmal, and Brooks, John. Tue .
"Techniques for storing data to enhance recovery and detection of data corruption errors". United States. https://www.osti.gov/servlets/purl/2293731.
@article{osti_2293731,
title = {Techniques for storing data to enhance recovery and detection of data corruption errors},
author = {Mills, Peter and Sullivan, Michael and Saxena, Nirmal and Brooks, John},
abstractNote = {Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {10}
}
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Works referenced in this record:
Dual Data Rate Bridge Controller with One-Step Majority Logic Decodable Codes for Multiple Bit Error Corrections with Low Latency
patent-application, September 2014
- Nemazie, Siamack; Tadepalli, Ravishankar; Asnaashari, Mehdi
- US Patent Application 14/217268; 20140281680
Communication Apparatus, Transmitter, Receiver, and Error Correction Optical Communication System
patent-application, May 2007
- Mizuochi, Takashi; Suzuki, Naoki; Kozaki, Seiji
- US Patent Application 11/278274; 20070104225
Method and apparatus for error detection and correction
patent, January 2019
- Rahul, Kumar; Perla, Amarnath; Yachareni, Santosh
- US Patent Document 10,177,794
Iterative Detector with ECC in Channel Domain
patent-application, November 2006
- Silvus, Gregory L.; Souvignier, Thomas V.
- US Patent Application 11/132414; 20060265634
Decoding Device, Decoding Method, and Recording and Reproducing Device
patent-application, December 2009
- Kanaoka, Toshikazu
- US Patent Application 12/385070; 20090307561
Inline Error Detection and Correction Techniques
patent-application, May 2018
- Wasserman, Michael; Mandal, Manas; Molnar, Steven
- US Patent Application 15/340919; 20180121287
Forward error correction for video signals
patent, January 2004
- Abbott, Liston; Jonnalagadda, Krishnamurthy
- US Patent Document 6,681,362
System and Method of Interfacing Co-Processors and Input/Output Devices Via a Main Memory System
patent-application, August 2012
- Takefman, Michael L.; Amer, Maher; Badalone, Riccardo
- US Patent Application 13/303048; 20120204079
Configurable De-Interleaver Design
patent-application, May 2007
- Su, Ling; Hammerschmidt, Joachim S.
- US Patent Application 11/595618; 20070110178
Providing error checking and correcting (ECC) capability for memory
patent, November 2015
- Zhu, Jun; Cao, Joseph Jun
- US Patent Document 9,183,078
Communications System Supporting Multiple Sector Sizes
patent-application, April 2012
- Gunnam, Kiran
- US Patent Application 12/910993; 20120099670
Communications System Employing Local and Global Interleaving/De-Interleaving
patent-application, March 2012
- Gunnam, Kiran; Han, Yang
- US Patent Application 12/891161; 20120079340
Implementing User Mode Foreign Device attachment to Memory Channel
patent-application, July 2014
- Abali, Bulent; Franceschini, Michele M.; Lastras-Montano, Luis A.
- US Patent Application 13/738035; 20140195765
Computing System and Data Transferring Method Thereof
patent-application, January 2017
- Lim, Sun-Young; Kim, Taeksoo; Kim, Indong
- US Patent Application 15/152029; 20170024162
DS-CDMA transmission method
patent, January 2005
- Okawa, Koichi; Ohno, Koji; Sawahashi, Mamoru
- US Patent Document 6,842,442