Three dimensional vertically structured electronic devices
Abstract
In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 2222239
- Patent Number(s):
- 11742424
- Application Number:
- 17/143,972
- Assignee:
- Lawrence Livermore National Security, LLC (Livermore, CA)
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 01/07/2021
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca, Shao, Qinghui, and Voss, Lars. Three dimensional vertically structured electronic devices. United States: N. p., 2023.
Web.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca, Shao, Qinghui, & Voss, Lars. Three dimensional vertically structured electronic devices. United States.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca, Shao, Qinghui, and Voss, Lars. Tue .
"Three dimensional vertically structured electronic devices". United States. https://www.osti.gov/servlets/purl/2222239.
@article{osti_2222239,
title = {Three dimensional vertically structured electronic devices},
author = {Conway, Adam and Harrison, Sara Elizabeth and Nikolic, Rebecca and Shao, Qinghui and Voss, Lars},
abstractNote = {In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {8}
}
Works referenced in this record:
Three dimensional vertically structured MISFET/MESFET
patent, January 2021
- Conway, Adam; Harrison, Sara Elizabeth; Nikolic, Rebecca J.
- US Patent Document 10,903,371
Graded Heterojunction Nanowire Device
patent-application, May 2016
- Oxland, Richard Kenneth
- US Patent Application 14/554584; 20160149001