Distributed coherence directory subsystem with exclusive data regions
Abstract
A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 2222154
- Patent Number(s):
- 11726915
- Application Number:
- 16/821,632
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 03/17/2020
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Eckert, Yasuko, Steinman, Maurice B., and Raasch, Steven. Distributed coherence directory subsystem with exclusive data regions. United States: N. p., 2023.
Web.
Eckert, Yasuko, Steinman, Maurice B., & Raasch, Steven. Distributed coherence directory subsystem with exclusive data regions. United States.
Eckert, Yasuko, Steinman, Maurice B., and Raasch, Steven. Tue .
"Distributed coherence directory subsystem with exclusive data regions". United States. https://www.osti.gov/servlets/purl/2222154.
@article{osti_2222154,
title = {Distributed coherence directory subsystem with exclusive data regions},
author = {Eckert, Yasuko and Steinman, Maurice B. and Raasch, Steven},
abstractNote = {A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {8}
}
Works referenced in this record:
Cache Coherency Using Die-Stacked Memory Device with Logic Die
patent-application, June 2014
- Loh, Gabriel H.; Beckmann, Bradford M.; Hsu, Lisa R.
- US Patent Application 13/726146; 20140181417
System and Method for Coherency Filtering
patent-application, October 2005
- Shaw, Mark
- US Patent Application 10/831050; 20050240736
Distributed directory cache coherence multi-processor computer architecture
patent, April 2002
- Janakiraman, Gopalakrishnan; Hsu, Tsen-Gong Jim; Venkitakrishnan, Padmanabha
- US Patent Document 6,374,331
Distributed Cache Coherency Directory with Failure Redundancy
patent-application, June 2014
- Wicki, Thomas M.; Phillips, Stephen E.; Aneshansley, Nicholas E.
- US Patent Application 13/758491; 20140181420