Soft error-mitigating semiconductor design system and associated methods
Abstract
A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.
- Inventors:
- Issue Date:
- Research Org.:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1987180
- Patent Number(s):
- 11593542
- Application Number:
- 17/187,516
- Assignee:
- Fermi Research Alliance, LLC (Batavia, IL)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC02-07CH11359
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 02/26/2021
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Miryala, Sandeep, Hoff, James R., and Deptuch, Grzegorz W. Soft error-mitigating semiconductor design system and associated methods. United States: N. p., 2023.
Web.
Miryala, Sandeep, Hoff, James R., & Deptuch, Grzegorz W. Soft error-mitigating semiconductor design system and associated methods. United States.
Miryala, Sandeep, Hoff, James R., and Deptuch, Grzegorz W. Tue .
"Soft error-mitigating semiconductor design system and associated methods". United States. https://www.osti.gov/servlets/purl/1987180.
@article{osti_1987180,
title = {Soft error-mitigating semiconductor design system and associated methods},
author = {Miryala, Sandeep and Hoff, James R. and Deptuch, Grzegorz W.},
abstractNote = {A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {2}
}
Works referenced in this record:
On-Chip Characterization of Single-Event Transient Pulsewidths
journal, December 2006
- Narasimham, Balaji; Ramachandran, Vishwa; Bhuva, Bharat L.
- IEEE Transactions on Device and Materials Reliability, Vol. 6, Issue 4
Robust Scan Synthesis for Protecting Soft Errors
patent-application, January 2011
- Wang, Lauhg-Terng; Touba, Nur A.; Jiang, Zhigang
- US Patent Application 12/508977; 20110022908
In-Place Resynthesis and Remapping Techniques for Soft Error Mitigation in FPGA
patent-application, November 2013
- He, Lei; Lee, Ju-Yueh; Feng, Zhe
- US Patent Application 13/850898; 20130305199
Simulation Methods and Systems for Predicting SER
patent-application, May 2018
- Monga, Udit; Jeon, Jong Wook; Machida, Ken
- US Patent Application 15/645227; 20180121587
Techniques for generating physical layouts of in silico multi mode integrated circuits
patent, August 2017
- Clark, Lawrence T.; Patterson, Dan; Ramamurthy, Chandarasekaran
- US Patent Document 9,734,272
Apparatus and Method for Protecting Soft Errors
patent-application, January 2011
- Wang, Laung-Terng; Touba, Nur A.; Jiang, Zhigang
- US Patent Application 12/509019; 20110022909
Safe Start-Up of a Network
patent-application, May 2009
- Steiner, Wilfried; Angelow, Harald; Bauer, Guenther
- US Patent Application 11/993995; 20090122812
Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process
conference, May 2019
- Miryala, Sandeep; Hemperek, Tomasz; Menouni, Mohsine
- Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)