Adaptive cache management based on programming model information
Abstract
A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1987152
- Patent Number(s):
- 11586539
- Application Number:
- 16/713,940
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 12/13/2019
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Na, Weon Taek, Kotra, Jagadish B., Eckert, Yasuko, Raasch, Steven, and Blagodurov, Sergey. Adaptive cache management based on programming model information. United States: N. p., 2023.
Web.
Na, Weon Taek, Kotra, Jagadish B., Eckert, Yasuko, Raasch, Steven, & Blagodurov, Sergey. Adaptive cache management based on programming model information. United States.
Na, Weon Taek, Kotra, Jagadish B., Eckert, Yasuko, Raasch, Steven, and Blagodurov, Sergey. Tue .
"Adaptive cache management based on programming model information". United States. https://www.osti.gov/servlets/purl/1987152.
@article{osti_1987152,
title = {Adaptive cache management based on programming model information},
author = {Na, Weon Taek and Kotra, Jagadish B. and Eckert, Yasuko and Raasch, Steven and Blagodurov, Sergey},
abstractNote = {A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {2}
}
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