Branch target filtering based on memory region access count
Abstract
A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1987028
- Patent Number(s):
- 11550588
- Application Number:
- 16/109,195
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 08/22/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Kalamatianos, John, Yalavarti, Adithya, Agrawal, Varun, Pal, Subhankar, and Srinivasan, Vinesh. Branch target filtering based on memory region access count. United States: N. p., 2023.
Web.
Kalamatianos, John, Yalavarti, Adithya, Agrawal, Varun, Pal, Subhankar, & Srinivasan, Vinesh. Branch target filtering based on memory region access count. United States.
Kalamatianos, John, Yalavarti, Adithya, Agrawal, Varun, Pal, Subhankar, and Srinivasan, Vinesh. Tue .
"Branch target filtering based on memory region access count". United States. https://www.osti.gov/servlets/purl/1987028.
@article{osti_1987028,
title = {Branch target filtering based on memory region access count},
author = {Kalamatianos, John and Yalavarti, Adithya and Agrawal, Varun and Pal, Subhankar and Srinivasan, Vinesh},
abstractNote = {A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2023},
month = {1}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Branch Prediction Apparatus and Method for Low Power Consumption
patent-application, March 2005
- Chung, Sung-Woo
- US Patent Application 10/947,278
Branch Prediction Power Reduction
patent-application, October 2013
- Aggarwal, Aneesh; Segelken, Ross; Wasson, Paul
- US Patent Application 13/458513; 20130290676
Asynchronous Lookahead Second Level Branch Target Buffer
patent-application, December 2013
- Bonanno, James J.; Giri, Akash V.; Mayer, Ulrich
- US Patent Application 13/524311; 20130339695
An Energy-Efficient Branch Prediction with Grouped Global History
conference, September 2015
- Huang, Mingkai; He, Dan; Liu, Xianhua
- 2015 44th International Conference on Parallel Processing
Dynamically enabled branch prediction
patent, June 2018
- Zhang, Haowei; Shen, Xiaoying; Shah, Manish K.
- US Patent Document 10,001,998
Second-Level Branch Target Buffer Bulk Transfer Filtering
patent-application, December 2013
- Bonanno, James J.; Mayer, Ulrich; Prasky, Brian R.
- US Patent Application 13/524306; 20130339693
Performance of Processors is Improved by Limiting Number of Branch Prediction Levels
patent-application, June 2013
- Bell, Jr., Robert H.; Chen, Wen-Tzer T.
- US Patent Application 13/308696; 20130145135
Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches
patent, August 2001
- Musoll, Enrique
- US Patent Document 6,282,614
Branch Prediction Using Multiple Versions of History Data
patent-application, November 2015
- Levitan, David S.; Moreira, Jose E.; Serrano, Mauricio J.
- US Patent Application 14/278000; 20150331691
Branch Prediction Suppression
patent-application, April 2016
- Filippo, Michael Alan; Elwood, Matthew Paul; Farooq, Umar
- US Patent Application 14/519697; 20160110202
Branch Predictor with Jump Ahead Logic to Jump Over Portions of Program Code Lacking Branches
patent-application, December 2012
- Xekalakis, Polychronis; Marcuello, Pedro; Latorre, Fernando
- US Patent Application 13/150970; 20120311308
Multiple-Table Branch Target Buffer
patent-application, January 2020
- Clouqueur, Thomas; Jarvis, Anthony
- US Patent Application 16/030031; 20200012497
Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch
patent, March 2010
- Schuler, Sergio; Snyder, Michael D.; Robinson, Leick D.
- US Patent Document 7,681,021
Power Management of Branch Predictors in a Computer Processor
patent-application, November 2017
- Levitan, David S.; Orzol, Nicholas R.; Philhower, Robert A.
- US Patent Application 15/220986; 20170344372
Unnecessary Dynamic Branch Prediction Elimination Method for Low-Power
patent-application, June 2007
- Chiao, Wei-Hau; Hu, Yau-Chong; Chung, Chung-Ping
- US Patent Application 11/450505; 20070130450