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Title: Compressing micro-operations in scheduler entries in a processor

Abstract

An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

Inventors:
; ;
Issue Date:
Research Org.:
Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1986852
Patent Number(s):
11513802
Application Number:
17/033,883
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 09/27/2020
Country of Publication:
United States
Language:
English

Citation Formats

Boyer, Michael W., Kalamatianos, John, and Majumder, Pritam. Compressing micro-operations in scheduler entries in a processor. United States: N. p., 2022. Web.
Boyer, Michael W., Kalamatianos, John, & Majumder, Pritam. Compressing micro-operations in scheduler entries in a processor. United States.
Boyer, Michael W., Kalamatianos, John, and Majumder, Pritam. Tue . "Compressing micro-operations in scheduler entries in a processor". United States. https://www.osti.gov/servlets/purl/1986852.
@article{osti_1986852,
title = {Compressing micro-operations in scheduler entries in a processor},
author = {Boyer, Michael W. and Kalamatianos, John and Majumder, Pritam},
abstractNote = {An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {11}
}

Works referenced in this record:

Generating and Performing Dependency Controlled Flow Comprising Multiple Micro-Operations (UOPS)
patent-application, December 2009


Managing an Issue Queue for Fused Instructions and Paired Instructions in a Microprocessor
patent-application, February 2019


Low Power Back-to-Back Wake up and Issue for Paired Issue Queue in a Microprocessor
patent-application, February 2020