Masked fault detection for reliable low voltage cache operation
Abstract
Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.
- Inventors:
- Issue Date:
- Research Org.:
- Advanced Micro Devices, Inc., Santa Clara, CA (United States); Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1986850
- Patent Number(s):
- 11509333
- Application Number:
- 17/125,145
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 12/17/2020
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Ganapathy, Shrikanth, and Kalamatianos, John. Masked fault detection for reliable low voltage cache operation. United States: N. p., 2022.
Web.
Ganapathy, Shrikanth, & Kalamatianos, John. Masked fault detection for reliable low voltage cache operation. United States.
Ganapathy, Shrikanth, and Kalamatianos, John. Tue .
"Masked fault detection for reliable low voltage cache operation". United States. https://www.osti.gov/servlets/purl/1986850.
@article{osti_1986850,
title = {Masked fault detection for reliable low voltage cache operation},
author = {Ganapathy, Shrikanth and Kalamatianos, John},
abstractNote = {Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {11}
}
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