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Title: GPU cache management based on locality type detection

Abstract

Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1986767
Patent Number(s):
11487671
Application Number:
16/446,119
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/19/2019
Country of Publication:
United States
Language:
English

Citation Formats

Zhang, Xianwei, Kalamatianos, John, and Beckmann, Bradford. GPU cache management based on locality type detection. United States: N. p., 2022. Web.
Zhang, Xianwei, Kalamatianos, John, & Beckmann, Bradford. GPU cache management based on locality type detection. United States.
Zhang, Xianwei, Kalamatianos, John, and Beckmann, Bradford. Tue . "GPU cache management based on locality type detection". United States. https://www.osti.gov/servlets/purl/1986767.
@article{osti_1986767,
title = {GPU cache management based on locality type detection},
author = {Zhang, Xianwei and Kalamatianos, John and Beckmann, Bradford},
abstractNote = {Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {11}
}

Works referenced in this record:

An efficient compiler framework for cache bypassing on GPUs
conference, November 2013


Issue Control for Multithreaded Processing
patent-application, April 2016


Priority-based cache allocation in throughput processors
conference, February 2015


Cache utilization and eviction based on allocated priority tokens
patent, October 2016


Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
conference, June 2017


Adaptive Cache Management for Energy-Efficient GPU Computing
conference, December 2014


Issue control for multithreaded processing
patent, February 2018


Scheduling Method and Processing Device Using the Same
patent-application, May 2017


Adaptive GPU cache bypassing
conference, February 2015


Computing System and Method for Processing Operations Thereof
patent-application, March 2017


Techniques for Accessing Content-Addressable Memory
patent-application, June 2014


Cache access detection and prediction
patent, July 2020


Space/time trade-offs in hash coding with allowable errors
journal, July 1970