Preemptive signal integrity control
Abstract
Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1986766
- Patent Number(s):
- 11487605
- Application Number:
- 15/921,489
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 03/14/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Roberts, David A., and Gonzales, Dean E. Preemptive signal integrity control. United States: N. p., 2022.
Web.
Roberts, David A., & Gonzales, Dean E. Preemptive signal integrity control. United States.
Roberts, David A., and Gonzales, Dean E. Tue .
"Preemptive signal integrity control". United States. https://www.osti.gov/servlets/purl/1986766.
@article{osti_1986766,
title = {Preemptive signal integrity control},
author = {Roberts, David A. and Gonzales, Dean E.},
abstractNote = {Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {11}
}
Works referenced in this record:
Bus system optimization
patent, November 2003
- Zerbe, Jared L.; Donnelly, Kevin S.; Sidiropoulos, Stefanos
- US Patent Document 6,643,787
System and Method for Event Monitoring and Error Detecton
patent-application, December 2002
- Kurrasch, Peter
- US Patent Application 09/873489; 20020184568
Method and System for Identifying Systemic Failures and Root Causes of Incidents
patent-application, December 2010
- Laberge, Jason; Bullemer, Peter
- US Patent Application 12/478071; 20100312522
Connector with Structures for Bi-Lateral Decoupling of a Hardware Interface
patent-application, January 2018
- Phares, Charles C.; Ceurter, Kevin J.
- US Patent Application 15/201312; 20180007788
System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities
patent, December 2005
- Kim, Youngsik; Lee, Yun Tae
- US Patent Document 6,976,108
Power Clamp for On-Chip ESD Protection
patent-application, February 2009
- Zhang, Jiong
- US Patent Application 12/221286; 20090040671