Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency
Abstract
A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE National Nuclear Security Administration (NNSA)
- OSTI Identifier:
- 1986674
- Patent Number(s):
- 11469765
- Application Number:
- 17/469,023
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- DOE Contract Number:
- NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 09/08/2021
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Brady, Charles E., and Loui, Hung. Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency. United States: N. p., 2022.
Web.
Brady, Charles E., & Loui, Hung. Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency. United States.
Brady, Charles E., and Loui, Hung. Tue .
"Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency". United States. https://www.osti.gov/servlets/purl/1986674.
@article{osti_1986674,
title = {Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency},
author = {Brady, Charles E. and Loui, Hung},
abstractNote = {A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {10}
}
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