Title: Offset-aligned three-dimensional integrated circuit

Abstract

A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

Inventors:

Wilkerson, Brett P.; Bhagavat, Milind S.; Agarwal, Rahul; Yudanov, Dmitri

Issue Date:

2022-09-06

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1925075

Patent Number(s):

11437359

Application Number:

16/799,243

Assignee:

Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/56 - Encapsulations, e.g. encapsulation layers, coatings
H01L21/6835 - {using temporarily an auxiliary support}
H01L21/76898 - {formed through a semiconductor substrate}
H01L21/78 - with subsequent division of the substrate into plural individual devices
H01L2221/68304 - using temporarily an auxiliary support
H01L2221/68368 - used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
H01L2221/68381 - Details of chemical or physical process used for separating the auxiliary support from a device or wafer
H01L2224/03 - Manufacturing methods
H01L2224/03002 - for supporting the semiconductor or solid-state body
H01L2224/0557 - the external layer being disposed on a via connection of the semiconductor or solid-state body
H01L2224/06179 - Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
H01L2224/06181 - On opposite sides of the body
H01L2224/08146 - the bonding area connecting to a via connection in the body
H01L2224/09179 - Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
H01L2224/13025 - the bump connector being disposed on a via connection of the semiconductor or solid-state body
H01L2224/16145 - the bodies being stacked
H01L2224/16225 - the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L2224/16227 - the bump connector connecting to a bond pad of the item
H01L2224/1703 - Bump connectors having different sizes, e.g. different diameters, heights or widths
H01L2224/17181 - On opposite sides of the body
H01L2224/2919 - with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
H01L2224/32145 - the bodies being stacked
H01L2224/32225 - the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L2224/73204 - the bump connector being embedded into the layer connector
H01L2224/81 - using a bump connector
H01L2224/81005 - being a temporary or sacrificial substrate
H01L2224/83 - using a layer connector
H01L2224/83005 - being a temporary or sacrificial substrate
H01L2224/92 - Specific sequence of method steps
H01L2225/06513 - Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
H01L2225/06562 - at least one device in the stack being rotated or offset
H01L2225/06575 - Auxiliary carrier between devices, the carrier having no electrical connection structure
H01L2225/06589 - Thermal management, e.g. cooling
H01L23/367 - Cooling facilitated by shape of device {
H01L23/3675 - {characterised by the shape of the housing}
H01L23/373 - Cooling facilitated by selection of materials for the device {or materials for thermal expansion adaptation, e.g. carbon}
H01L23/3737 - {Organic materials with or without a thermoconductive filler}
H01L23/481 - {Internal lead connections, e.g. via connections, feedthrough structures}
H01L24/03 - {Manufacturing methods}
H01L24/05 - {of an individual bonding area}
H01L24/06 - {of a plurality of bonding areas}
H01L24/08 - {of an individual bonding area}
H01L24/09 - {of a plurality of bonding areas}
H01L24/13 - {of an individual bump connector}
H01L24/16 - {of an individual bump connector}
H01L24/17 - {of a plurality of bump connectors}
H01L24/29 - {of an individual layer connector}
H01L24/32 - {of an individual layer connector}
H01L24/81 - {using a bump connector}
H01L24/83 - {using a layer connector}
H01L24/92 - {Specific sequence of method steps}
H01L25/18 - the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00 {
H01L25/50 - {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
H01L2924/00 - Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/00012 - Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
H01L2924/0665 - Epoxy resin
H01L2924/1431 - Logic devices
H01L2924/1433 - Application-specific integrated circuit [ASIC]
H01L2924/1434 - Memory

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DOE Contract Number:  

AC52-07NA27344; B620717

Resource Type:

Patent

Resource Relation:

Patent File Date: 02/24/2020

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING