Techniques for improving operand caching

Gutierrez, Anthony T.; Beckmann, Bradford M.; Chow, Marcus Nathaniel

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Title: Techniques for improving operand caching

Abstract

A technique for determining whether a register value should be written to an operand cache or whether the register value should remain in and not be evicted from the operand cache is provided. The technique includes executing an instruction that accesses an operand that comprises the register value, performing one or both of a lookahead technique and a prediction technique to determine whether the register value should be written to an operand cache or whether the register value should remain in and not be evicted from the operand cache, and based on the determining, updating the operand cache.

Inventors:: Gutierrez, Anthony T.; Beckmann, Bradford M.; Chow, Marcus Nathaniel

Issue Date:: 2022-09-06

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1925068

Patent Number(s):: 11436016

Application Number:: 16/703,833

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/30047 - {Prefetch instructions
G06F9/30098 - {Register arrangements}
G06F9/30145 - {Instruction analysis, e.g. decoding, instruction word fields}
G06F9/3832 - {Value prediction for operands
G06F9/3838 - {Dependency mechanisms, e.g. register scoreboarding}
G06F9/3844 - {using dynamic prediction, e.g. branch history table}
G06F9/3851 - {from multiple instruction streams, e.g. multistreaming
G06F9/3887 - {controlled by a single instruction, e.g. SIMD}

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 12/04/2019

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Gutierrez, Anthony T., Beckmann, Bradford M., and Chow, Marcus Nathaniel. Techniques for improving operand caching.  United States: N. p., 2022. 
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                    Gutierrez, Anthony T., Beckmann, Bradford M., & Chow, Marcus Nathaniel. Techniques for improving operand caching.  United States.

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                    Gutierrez, Anthony T., Beckmann, Bradford M., and Chow, Marcus Nathaniel. Tue .  
        "Techniques for improving operand caching".  United States.  https://www.osti.gov/servlets/purl/1925068.

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@article{osti_1925068,

  title        = {Techniques for improving operand caching},

  author       = {Gutierrez, Anthony T. and Beckmann, Bradford M. and Chow, Marcus Nathaniel},

  abstractNote = {A technique for determining whether a register value should be written to an operand cache or whether the register value should remain in and not be evicted from the operand cache is provided. The technique includes executing an instruction that accesses an operand that comprises the register value, performing one or both of a lookahead technique and a prediction technique to determine whether the register value should be written to an operand cache or whether the register value should remain in and not be evicted from the operand cache, and based on the determining, updating the operand cache.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2022},

  month        = {9}

}

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Works referenced in this record:

Intelligent caching for an operand cache
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Olson, Timothy A.; Potter, Terence M.; Blomgren, James S.
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Pipelined allocation for operand cache
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Kenney, Robert D.; Potter, Terence M.; Havlir, Andrew M.
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Reuse Aware Cache Line Insertion and Victim Selection in Large Cache Memory
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Havlir, Andrew M.; Potter, Terence M.
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Similar Records

Title: Techniques for improving operand caching

Abstract

Citation Formats

Intelligent caching for an operand cache patent, October 2016

Computing apparatus and method for cache management patent, April 2019

Use-Based Register Caching with Decoupled Indexing journal, March 2004

Automatic pattern-based operand prefetching patent, February 2015

Instructions and logic to provide advanced paging capabilities for secure enclave page caches patent, August 2016

Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory patent, September 2020

Magnetoresistive random-access memory cache write management patent, December 2018

Cache eviction based on types of data stored in storage systems patent, February 2017

Hint values for use with an operand cache patent, May 2017

Pipelined allocation for operand cache patent, June 2020

Reuse Aware Cache Line Insertion and Victim Selection in Large Cache Memory patent-application, March 2019

Cache memory unit including a replacement address register and address update circuitry for reduced cache overhead patent, July 1996

Operand cache flush, eviction, and clean techniques using hint information and dirty information patent, April 2017

Cache organization and method patent, August 2017

Cache eviction using memory entry value patent, March 2013

Intelligent caching for an operand cache
patent, October 2016

Computing apparatus and method for cache management
patent, April 2019

Use-Based Register Caching with Decoupled Indexing
journal, March 2004

Automatic pattern-based operand prefetching
patent, February 2015

Instructions and logic to provide advanced paging capabilities for secure enclave page caches
patent, August 2016

Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory
patent, September 2020

Magnetoresistive random-access memory cache write management
patent, December 2018

Cache eviction based on types of data stored in storage systems
patent, February 2017

Hint values for use with an operand cache
patent, May 2017

Pipelined allocation for operand cache
patent, June 2020

Reuse Aware Cache Line Insertion and Victim Selection in Large Cache Memory
patent-application, March 2019

Cache memory unit including a replacement address register and address update circuitry for reduced cache overhead
patent, July 1996

Operand cache flush, eviction, and clean techniques using hint information and dirty information
patent, April 2017

Cache organization and method
patent, August 2017

Cache eviction using memory entry value
patent, March 2013