DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Defense mechanism for non-volatile memory based main memory

Abstract

A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Device, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1924995
Patent Number(s):
11416323
Application Number:
16/723,855
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/20/2019
Country of Publication:
United States
Language:
English

Citation Formats

SeyedzadehDelcheh, SeyedMohammad, and Raasch, Steven. Defense mechanism for non-volatile memory based main memory. United States: N. p., 2022. Web.
SeyedzadehDelcheh, SeyedMohammad, & Raasch, Steven. Defense mechanism for non-volatile memory based main memory. United States.
SeyedzadehDelcheh, SeyedMohammad, and Raasch, Steven. Tue . "Defense mechanism for non-volatile memory based main memory". United States. https://www.osti.gov/servlets/purl/1924995.
@article{osti_1924995,
title = {Defense mechanism for non-volatile memory based main memory},
author = {SeyedzadehDelcheh, SeyedMohammad and Raasch, Steven},
abstractNote = {A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Aug 16 00:00:00 EDT 2022},
month = {Tue Aug 16 00:00:00 EDT 2022}
}

Works referenced in this record:

DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells
journal, December 2019


Improving write operations in MLC phase change memory
conference, February 2012


Memory device, operating and control method thereof
patent, February 2017


ADAM: Architecture for write disturbance mitigation in scaled phase change memory
conference, March 2018


Modeling of Programming and Read Performance in Phase-Change Memories—Part I: Cell Optimization and Scaling
journal, February 2008


A durable and energy efficient main memory using phase change memory technology
conference, June 2009


Hardwired Remapped Memory
patent-application, August 2013


Memory Cell Presetting for Improved Memory Performance
patent-application, January 2013


Mitigating Write Disturbance in Super-Dense Phase Change Memories
conference, June 2014


Sd-Pcm
conference, March 2015

  • Wang, Rujia; Jiang, Lei; Zhang, Youtao
  • Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems
  • https://doi.org/10.1145/2694344.2694352