Memory access response merging in a memory hierarchy

Kayiran, Onur; Eckert, Yasuko; Oskin, Mark Henry; Loh, Gabriel H.; Raasch, Steven E.; Kazakov, Maxim V.

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A01 - agriculture
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Title: Memory access response merging in a memory hierarchy

Abstract

A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.

Inventors:: Kayiran, Onur; Eckert, Yasuko; Oskin, Mark Henry; Loh, Gabriel H.; Raasch, Steven E.; Kazakov, Maxim V.

Issue Date:: 2022-08-02

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1924944

Patent Number(s):: 11403221

Application Number:: 17/031,706

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/3037 - {where the computing system component is a memory, e.g. virtual memory, cache
G06F12/0811 - with multilevel cache hierarchies
G06F12/084 - with a shared cache
G06F12/0877 - Cache access modes
G06F12/0897 - with two or more cache hierarchy levels
G06F13/1668 - {Details of memory controller}
G06F2212/1021 - Hit rate improvement

Show less

DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/24/2020

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Kayiran, Onur, Eckert, Yasuko, Oskin, Mark Henry, Loh, Gabriel H., Raasch, Steven E., and Kazakov, Maxim V. Memory access response merging in a memory hierarchy.  United States: N. p., 2022. 
        Web.

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                    Kayiran, Onur, Eckert, Yasuko, Oskin, Mark Henry, Loh, Gabriel H., Raasch, Steven E., & Kazakov, Maxim V. Memory access response merging in a memory hierarchy.  United States.

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                    Kayiran, Onur, Eckert, Yasuko, Oskin, Mark Henry, Loh, Gabriel H., Raasch, Steven E., and Kazakov, Maxim V. Tue .  
        "Memory access response merging in a memory hierarchy".  United States.  https://www.osti.gov/servlets/purl/1924944.

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@article{osti_1924944,

  title        = {Memory access response merging in a memory hierarchy},

  author       = {Kayiran, Onur and Eckert, Yasuko and Oskin, Mark Henry and Loh, Gabriel H. and Raasch, Steven E. and Kazakov, Maxim V.},

  abstractNote = {A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2022},

  month        = {8}

}

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Similar Records

Title: Memory access response merging in a memory hierarchy

Abstract

Citation Formats

Processor memory system patent, December 2017

Network switch having a programmable counter patent, February 2006

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system patent, May 1999

Method for signaling in a high speed communication system patent, May 2002

Fast round robin priority port scheduler for high capacity ATM switches patent, April 2003

Configurable cache for multi-endpoint heterogeneous coherent system patent-application, April 2020

Multiprocessor node controller circuit and method patent, June 2004

Using a second content-addressable memory to manage memory burst accesses in memory sub-systems patent-application, June 2020

System and method for traffic shaping packet-based signals patent, December 2003

Interleaved weighted fair queuing mechanism and system patent, December 2005

System and method for a quality of service in a multi-layer network element patent, September 2005

Method for avoiding out-of-ordering of frames in a network switch patent, December 2006

Broadcast command and response patent-application, March 2020

Network switch with broadcast support patent, July 1998

Arbitration mechanism for a multicast logic engine of a switching fabric circuit patent, April 1999

Communication network across which packets of data are transmitted according to a priority scheme patent, November 2003

Apparatus and method for traffic shaping in a network switch patent, July 2004

Method for load balancing in a network switch patent, October 2005

Apparatus and methods to change thresholds to control congestion in ATM switches patent, May 1999

Modular input/output controller capable of routing packets over busses operating at different speeds patent, April 2003

Distributing ATM cells to output ports based upon destination information using ATM switch core and IP forwarding patent, August 2004

Architecture for high speed class of service enabled linecard patent, February 2004

Multi-interface symmetric multiprocessor patent, November 2002

Isochronous switched fabric network patent, February 2006

Means And Apparatus For A Scalable Congestion Free Switching System With Intelligent Control patent-application, February 2003

Supporting responses for memory types with non-uniform latencies on same channel patent, April 2019

Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory patent, October 1999

Switching device and method for controlling the routing of data packets patent, February 2006

High bandwidth PCI to packet switched router bridge having minimized memory latency patent, June 1999

Switch fabric with path redundancy patent, September 2005

Distributed type switching system patent, October 2001

Multicasting using a wormhole routing switching element patent, April 2003

Packet switch for switching variable length packets in the form of ATM cells patent, June 2005

Scheduler for an information packet switch patent, September 2001

Apparatus and method for managing memory in a network switch patent, June 2005

Message Broadcast with Router Bypassing patent-application, December 2011

Data-transfer routing management for packet-oriented digital communication system including ATM networks patent, August 1995

System and method for broadcasting data to multiple hardware forwarding engines patent, November 2017

Method and apparatus for routing packets that have multiple destinations patent, September 2007

Packet switching apparatus and method in data network patent, June 2004

Flow control arrangement for the transmission of data packets to a communication network patent, February 1988

Traffic manager for network switch port patent, October 2005

Memory Blockade for Verifying System Security with Respect to Speculative Execution patent-application, March 2021

Methods and systems to transfer information using an alternative routing associated with a communication network patent, September 2005

Asynchronous transfer mode switch utilizing optical wave division multiplexing patent, July 2002

Segmentation and reassembly of data frames patent, September 2003

Layer one switching in a packet, cell, or frame-based network patent, August 2003

Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode patent, January 1995

Wavelength division multiplexing combined with time division multiplexing using a common time reference patent, January 2004

Multicast copy ring for database direct memory access filtering engine patent, October 2019

Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels patent, July 2004

Network for transferring consecutive packets between processor and memory with a reduced blocking time patent, January 1999

System architecture for and method of dual path data processing and management of packets and/or cells and the like patent, June 1999

Intelligent interleaving scheme for multibank memory patent, June 2004

Method and apparatus for coordinating access to an output of a routing device in a packet switching network patent, April 1999

Method and apparatus for wire speed IP multicast forwarding patent, June 2004

Apparatus and method for optimizing access to memory patent, May 2004

Processor memory system
patent, December 2017

Network switch having a programmable counter
patent, February 2006

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
patent, May 1999

Method for signaling in a high speed communication system
patent, May 2002

Fast round robin priority port scheduler for high capacity ATM switches
patent, April 2003

Configurable cache for multi-endpoint heterogeneous coherent system
patent-application, April 2020

Multiprocessor node controller circuit and method
patent, June 2004

Using a second content-addressable memory to manage memory burst accesses in memory sub-systems
patent-application, June 2020

System and method for traffic shaping packet-based signals
patent, December 2003

Interleaved weighted fair queuing mechanism and system
patent, December 2005

System and method for a quality of service in a multi-layer network element
patent, September 2005

Method for avoiding out-of-ordering of frames in a network switch
patent, December 2006

Broadcast command and response
patent-application, March 2020

Network switch with broadcast support
patent, July 1998

Arbitration mechanism for a multicast logic engine of a switching fabric circuit
patent, April 1999

Communication network across which packets of data are transmitted according to a priority scheme
patent, November 2003

Apparatus and method for traffic shaping in a network switch
patent, July 2004

Method for load balancing in a network switch
patent, October 2005

Apparatus and methods to change thresholds to control congestion in ATM switches
patent, May 1999

Modular input/output controller capable of routing packets over busses operating at different speeds
patent, April 2003

Distributing ATM cells to output ports based upon destination information using ATM switch core and IP forwarding
patent, August 2004

Architecture for high speed class of service enabled linecard
patent, February 2004

Multi-interface symmetric multiprocessor
patent, November 2002

Isochronous switched fabric network
patent, February 2006

Means And Apparatus For A Scalable Congestion Free Switching System With Intelligent Control
patent-application, February 2003

Supporting responses for memory types with non-uniform latencies on same channel
patent, April 2019

Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory
patent, October 1999

Switching device and method for controlling the routing of data packets
patent, February 2006

High bandwidth PCI to packet switched router bridge having minimized memory latency
patent, June 1999

Switch fabric with path redundancy
patent, September 2005

Distributed type switching system
patent, October 2001

Multicasting using a wormhole routing switching element
patent, April 2003

Packet switch for switching variable length packets in the form of ATM cells
patent, June 2005

Scheduler for an information packet switch
patent, September 2001

Apparatus and method for managing memory in a network switch
patent, June 2005

Message Broadcast with Router Bypassing
patent-application, December 2011

Data-transfer routing management for packet-oriented digital communication system including ATM networks
patent, August 1995

System and method for broadcasting data to multiple hardware forwarding engines
patent, November 2017

Method and apparatus for routing packets that have multiple destinations
patent, September 2007

Packet switching apparatus and method in data network
patent, June 2004

Flow control arrangement for the transmission of data packets to a communication network
patent, February 1988

Traffic manager for network switch port
patent, October 2005

Memory Blockade for Verifying System Security with Respect to Speculative Execution
patent-application, March 2021

Methods and systems to transfer information using an alternative routing associated with a communication network
patent, September 2005

Asynchronous transfer mode switch utilizing optical wave division multiplexing
patent, July 2002

Segmentation and reassembly of data frames
patent, September 2003

Layer one switching in a packet, cell, or frame-based network
patent, August 2003

Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode
patent, January 1995

Wavelength division multiplexing combined with time division multiplexing using a common time reference
patent, January 2004

Multicast copy ring for database direct memory access filtering engine
patent, October 2019

Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels
patent, July 2004

Network for transferring consecutive packets between processor and memory with a reduced blocking time
patent, January 1999

System architecture for and method of dual path data processing and management of packets and/or cells and the like
patent, June 1999

Intelligent interleaving scheme for multibank memory
patent, June 2004

Method and apparatus for coordinating access to an output of a routing device in a packet switching network
patent, April 1999

Method and apparatus for wire speed IP multicast forwarding
patent, June 2004

Apparatus and method for optimizing access to memory
patent, May 2004