Latency hiding for caches
Abstract
A technique for accessing a memory having a high latency portion and a low latency portion is provided. The technique includes detecting a promotion trigger to promote data from the high latency portion to the low latency portion, in response to the promotion trigger, copying cache lines associated with the promotion trigger from the high latency portion to the low latency portion, and in response to a read request, providing data from either or both of the high latency portion or the low latency portion, based on a state associated with data in the high latency portion and the low latency portion.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1924927
- Patent Number(s):
- 11397691
- Application Number:
- 16/683,142
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 11/13/2019
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Kalamatianos, John, Kokolis, Apostolos, and Ganapathy, Shrikanth. Latency hiding for caches. United States: N. p., 2022.
Web.
Kalamatianos, John, Kokolis, Apostolos, & Ganapathy, Shrikanth. Latency hiding for caches. United States.
Kalamatianos, John, Kokolis, Apostolos, and Ganapathy, Shrikanth. Tue .
"Latency hiding for caches". United States. https://www.osti.gov/servlets/purl/1924927.
@article{osti_1924927,
title = {Latency hiding for caches},
author = {Kalamatianos, John and Kokolis, Apostolos and Ganapathy, Shrikanth},
abstractNote = {A technique for accessing a memory having a high latency portion and a low latency portion is provided. The technique includes detecting a promotion trigger to promote data from the high latency portion to the low latency portion, in response to the promotion trigger, copying cache lines associated with the promotion trigger from the high latency portion to the low latency portion, and in response to a read request, providing data from either or both of the high latency portion or the low latency portion, based on a state associated with data in the high latency portion and the low latency portion.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {7}
}
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