Systems and methods for tensor scheduling
Abstract
A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.
- Inventors:
- Issue Date:
- Research Org.:
- Reservoir Labs, Inc., San Diego, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1893088
- Patent Number(s):
- 11372629
- Application Number:
- 16/852,867
- Assignee:
- Reservoir Labs, Inc. (San Diego, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- DOE Contract Number:
- SC0017071
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 04/20/2020
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Meister, Benoit J., and Papenhausen, Eric. Systems and methods for tensor scheduling. United States: N. p., 2022.
Web.
Meister, Benoit J., & Papenhausen, Eric. Systems and methods for tensor scheduling. United States.
Meister, Benoit J., and Papenhausen, Eric. Tue .
"Systems and methods for tensor scheduling". United States. https://www.osti.gov/servlets/purl/1893088.
@article{osti_1893088,
title = {Systems and methods for tensor scheduling},
author = {Meister, Benoit J. and Papenhausen, Eric},
abstractNote = {A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {6}
}
Works referenced in this record:
Methods and apparatus for joint scheduling and layout optimization to enable multi-level vectorization
patent, November 2016
- Baskaran, Muthu M.; Lethin, Richard A.; Meister, Benoit J.
- US Patent Document 9,489,180
Method And Apparatus For Generating Check Matrix
patent-application, November 2005
- Matsumoto, Wataru
- US Patent Application 10/520061; 20050251724 A1
Systems and Methods for Footprint Based Scheduling
patent-application, April 2016
- Meister, Benoit J.; Baskaran, Muthu M.; Lethin, Richard A.
- US Patent Application 14/839539; 20160098257 A1
Information Processing Device and Information Processing Method
patent-application, August 2020
- Tsugane, Keisuke
- US Patent Application 16/744287; 20200249923 A1
Method and Apparatus for Converting Software
patent-application, November 2011
- Hedley, David; Rodriguez, Mark
- US Patent Application 12/772477; 20110271247 A1
Scheduling Computation Graphs Using Neural Networks
patent-application, September 2020
- Li, Yujia; Nair, Vinood; Gimeno, Gil
- US Patent Application 16/818932; 20200293838 A1