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Title: Systems and methods for tensor scheduling

Abstract

A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.

Inventors:
;
Issue Date:
Research Org.:
Reservoir Labs, Inc., San Diego, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1893088
Patent Number(s):
11372629
Application Number:
16/852,867
Assignee:
Reservoir Labs, Inc. (San Diego, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
DOE Contract Number:  
SC0017071
Resource Type:
Patent
Resource Relation:
Patent File Date: 04/20/2020
Country of Publication:
United States
Language:
English

Citation Formats

Meister, Benoit J., and Papenhausen, Eric. Systems and methods for tensor scheduling. United States: N. p., 2022. Web.
Meister, Benoit J., & Papenhausen, Eric. Systems and methods for tensor scheduling. United States.
Meister, Benoit J., and Papenhausen, Eric. Tue . "Systems and methods for tensor scheduling". United States. https://www.osti.gov/servlets/purl/1893088.
@article{osti_1893088,
title = {Systems and methods for tensor scheduling},
author = {Meister, Benoit J. and Papenhausen, Eric},
abstractNote = {A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {6}
}

Works referenced in this record:

Methods and apparatus for joint scheduling and layout optimization to enable multi-level vectorization
patent, November 2016


Method And Apparatus For Generating Check Matrix
patent-application, November 2005


Systems and Methods for Footprint Based Scheduling
patent-application, April 2016


Information Processing Device and Information Processing Method
patent-application, August 2020


Method and Apparatus for Converting Software
patent-application, November 2011


Scheduling Computation Graphs Using Neural Networks
patent-application, September 2020