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Title: Gated ring oscillator with constant dynamic power consumption

Abstract

A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

Inventors:
Issue Date:
Research Org.:
Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1892735
Patent Number(s):
11283430
Application Number:
16/916,473
Assignee:
Fermi Research Alliance, LLC (Batavia, IL)
Patent Classifications (CPCs):
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
DOE Contract Number:  
AC02-07CH11359
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/30/2020
Country of Publication:
United States
Language:
English

Citation Formats

Wu, Jinyuan. Gated ring oscillator with constant dynamic power consumption. United States: N. p., 2022. Web.
Wu, Jinyuan. Gated ring oscillator with constant dynamic power consumption. United States.
Wu, Jinyuan. Tue . "Gated ring oscillator with constant dynamic power consumption". United States. https://www.osti.gov/servlets/purl/1892735.
@article{osti_1892735,
title = {Gated ring oscillator with constant dynamic power consumption},
author = {Wu, Jinyuan},
abstractNote = {A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {3}
}

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