Mapping entry invalidation
Abstract
A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.
- Inventors:
- Issue Date:
- Research Org.:
- Hewlett Packard Enterprise Development LP, Houston, TX (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1892616
- Patent Number(s):
- 11249918
- Application Number:
- 16/174,738
- Assignee:
- Hewlett Packard Enterprise Development LP (Houston, TX)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 10/30/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Walker, Shawn K., Kroeger, Christopher Shawn, and Sherlock, Derek A. Mapping entry invalidation. United States: N. p., 2022.
Web.
Walker, Shawn K., Kroeger, Christopher Shawn, & Sherlock, Derek A. Mapping entry invalidation. United States.
Walker, Shawn K., Kroeger, Christopher Shawn, and Sherlock, Derek A. Tue .
"Mapping entry invalidation". United States. https://www.osti.gov/servlets/purl/1892616.
@article{osti_1892616,
title = {Mapping entry invalidation},
author = {Walker, Shawn K. and Kroeger, Christopher Shawn and Sherlock, Derek A.},
abstractNote = {A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {2}
}
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