Performance for GPU exceptions
Abstract
Techniques for improving performance of accelerated processing devices (“APDs”) when exceptions occur are provided. In APDs, the very large number of parallel processing execution units, and the complexity of the hardware used to execute a large number of work-items in parallel, means that APDs typically stall when an exception occurs (unlike in central processing units (“CPUs”), which are able to execute speculatively and out-of-order). However, the techniques provided herein allow at least some execution to occur past exceptions. Execution past an exception generating instruction occurs by executing instructions that would not lead to a corruption while skipping those that would lead to a corruption. After the exception has been satisfied, execution occurs in a replay mode in which the potentially exception-generating instruction is executed and in which instructions that did not execute in the exception-wait mode are executed. A mask and counter are used to control execution in replay mode.
- Inventors:
- Issue Date:
- Research Org.:
- Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1892615
- Patent Number(s):
- 11249765
- Application Number:
- 16/109,567
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G06 - COMPUTING G06T - IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 08/22/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Gutierrez, Anthony T. Performance for GPU exceptions. United States: N. p., 2022.
Web.
Gutierrez, Anthony T. Performance for GPU exceptions. United States.
Gutierrez, Anthony T. Tue .
"Performance for GPU exceptions". United States. https://www.osti.gov/servlets/purl/1892615.
@article{osti_1892615,
title = {Performance for GPU exceptions},
author = {Gutierrez, Anthony T.},
abstractNote = {Techniques for improving performance of accelerated processing devices (“APDs”) when exceptions occur are provided. In APDs, the very large number of parallel processing execution units, and the complexity of the hardware used to execute a large number of work-items in parallel, means that APDs typically stall when an exception occurs (unlike in central processing units (“CPUs”), which are able to execute speculatively and out-of-order). However, the techniques provided herein allow at least some execution to occur past exceptions. Execution past an exception generating instruction occurs by executing instructions that would not lead to a corruption while skipping those that would lead to a corruption. After the exception has been satisfied, execution occurs in a replay mode in which the potentially exception-generating instruction is executed and in which instructions that did not execute in the exception-wait mode are executed. A mask and counter are used to control execution in replay mode.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2022},
month = {2}
}
Works referenced in this record:
Method and Apparatus for Servicing Page Fault Exceptions
patent-application, June 2013
- Hartog, Robert Scott; Taylor, Ralph Clay; Mantor, Michael
- US Patent Application 13/311,829; 2013/0141446 Al
Instructions and Logic to Interrupt and Resume Paging in a Secure Enclave Page Cache
patent-application, December 2015
- Rozas, Carlos N.; Alexandrovich, Ilya; Neiger, Gilbert
- US Patent Application 14/318,508; 2015/0378941 Al
iGPU: Exception support and speculative execution on GPUs
conference, June 2012
- Menon, Jaikrishnan; de Kruijf, Marc; Sankaralingam, Karthikeyan
- 2012 39th Annual International Symposium on Computer Architecture (ISCA)
Towards high performance paged memory for GPUs
conference, March 2016
- Zheng, Tianhao; Nellans, David; Zulfiqar, Arslan
- 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design
conference, October 2016
- Rhu, Minsoo; Gimelshein, Natalia; Clemons, Jason
- 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Instruction and logic for interrupt and exception handling
patent, October 2019
- O'Connor, Richard B.; Strong, Beeman C.; Chynoweth, Michael W.
- US Patent Document 10,445,204
Efficient exception handling support for GPUs
conference, October 2017
- Tanasic, Ivan; Gelado, Isaac; Jorda, Marc
- Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture