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Title: Fiber attach enabled wafer level fanout

Abstract

A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

Inventors:
; ;
Issue Date:
Research Org.:
Ayar Labs, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1860030
Patent Number(s):
11163120
Application Number:
16/685,838
Assignee:
Ayar Labs, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G02 - OPTICS G02B - OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
AR0000850
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/15/2019
Country of Publication:
United States
Language:
English

Citation Formats

Ardalan, Shahab, Davenport, Michael, and Meade, Roy Edward. Fiber attach enabled wafer level fanout. United States: N. p., 2021. Web.
Ardalan, Shahab, Davenport, Michael, & Meade, Roy Edward. Fiber attach enabled wafer level fanout. United States.
Ardalan, Shahab, Davenport, Michael, and Meade, Roy Edward. Tue . "Fiber attach enabled wafer level fanout". United States. https://www.osti.gov/servlets/purl/1860030.
@article{osti_1860030,
title = {Fiber attach enabled wafer level fanout},
author = {Ardalan, Shahab and Davenport, Michael and Meade, Roy Edward},
abstractNote = {A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {11}
}

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