Title: Quality of service for input/output memory management unit

Abstract

A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

Inventors:

Basu, Arkaprava; LeBeane, Michael W.; Van Tassell, Eric

Issue Date:

2021-10-12

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1859944

Patent Number(s):

11144473

Application Number:

16/007,027

Assignee:

Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F11/3409 - {for performance assessment}
G06F11/3471 - {Address tracing}
G06F11/3485 - {for I/O devices}
G06F12/0842 - for multiprocessing or multitasking
G06F12/1009 - using page tables, e.g. page table structures
G06F12/1036 - for multiple virtual address spaces, e.g. segmentation
G06F12/1081 - for peripheral access to main memory, e.g. direct memory access [DMA]
G06F13/1626 - {by reordering requests}
G06F13/1642 - {with request queuing}
G06F13/225 - {with priority control}
G06F2201/81 - Threshold
G06F2201/88 - Monitoring involving counting
G06F2212/1041 - Resource optimization
G06F2212/502 - using adaptive policy
G06F2212/681 - Multi-level TLB, e.g. microTLB and main TLB
G06F9/4881 - {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
G06F9/5011 - {the resources being hardware resources other than CPUs, Servers and Terminals}

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DOE Contract Number:  

AC52-07NA27344; B620717

Resource Type:

Patent

Resource Relation:

Patent File Date: 06/13/2018

Country of Publication:

United States

Language:

English