DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Locality-aware and sharing-aware cache coherence for collections of processors

Abstract

A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.

Inventors:
;
Issue Date:
Research Org.:
Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1840447
Patent Number(s):
11119923
Application Number:
15/440,979
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
AC52-07NA27344; B608045
Resource Type:
Patent
Resource Relation:
Patent File Date: 02/23/2017
Country of Publication:
United States
Language:
English

Citation Formats

Farmahini Farahani, Amin, and Jayasena, Nuwan. Locality-aware and sharing-aware cache coherence for collections of processors. United States: N. p., 2021. Web.
Farmahini Farahani, Amin, & Jayasena, Nuwan. Locality-aware and sharing-aware cache coherence for collections of processors. United States.
Farmahini Farahani, Amin, and Jayasena, Nuwan. Tue . "Locality-aware and sharing-aware cache coherence for collections of processors". United States. https://www.osti.gov/servlets/purl/1840447.
@article{osti_1840447,
title = {Locality-aware and sharing-aware cache coherence for collections of processors},
author = {Farmahini Farahani, Amin and Jayasena, Nuwan},
abstractNote = {A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {9}
}

Works referenced in this record:

Active Memory Cube: A processing-in-memory architecture for exascale systems
journal, March 2015


System and Method for Promoting Reader Groups for Lock Cohorting
patent-application, August 2017


System and method for data forwarding in a programmable multiple network processor environment
patent, November 2005


Electronic Device and Method for Controlling Shareable Cache Memory Thereof
patent-application, June 2016


Implementing locks in a distributed processing system
patent, October 2002


Dynamic Releasing of Cache Lines
patent-application, March 2017


Method, Apparatus, and System for Speculative Execution Event Counter Checkpointing and Restoring
patent-application, June 2012


Methods and Processor for Processing Data
patent-application, October 2015


Cache Coherence for GPU Architectures
journal, May 2014


Fine-grained Hardware Transactional Lock Elision
patent-application, August 2016


Delayed consistency and its effects on the miss rate of parallel programs
conference, January 1991


Distributed Reservation Based Coherency Protocol
patent-application, March 2018


Cache allocation
patent-application, October 2004


Multi-core processors
patent-application, January 2014


System and Method for Simplifying Cache Coherence Using Multiple Write Policies
patent-application, September 2013


Method and Apparatus for Shared Line Unified Cache
patent-application, June 2015


Shared Memory Controller And Method Of Using Same
patent-application, January 2017


Fault tolerant mutual exclusion locks for shared memory systems
patent-application, March 2005


System, Method, and Apparatuses for Remote Monitoring
patent-application, June 2017


QuickRelease: A throughput-oriented approach to release consistency on GPUs
conference, February 2014


Access to Shared Memory Segments by Multiple Application Process
patent-application, February 2012


Convolutional Memory Integrity
patent-application, October 2017


Scope consistency
conference, January 1996


Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
conference, January 1995


Coherent shared memory processing system
patent, January 2007


Transaction based shared data operations in a multiprocessor environment
patent-application, July 2006


Technologies for Region Based Cache Management
patent-application, October 2017


Management of Shared Pipeline Resource Usage Based on Level Information
patent-application, December 2015


Electronic System Level Parallel Simulation Method with Detection of Conflicts of Access to a Shared Memory
patent-application, February 2019


Flushing Entries in a Non-Coherent Cache
patent-application, September 2014


Locality-Aware and Sharing-Aware Cache Coherence for Collections of Processors.
patent-application, August 2018


Mutual Exclusion in a Non-Coherent Memory Hierarchy
patent-application, October 2017


Broadcast invalidate scheme
patent-application, April 2004


Method and Apparatus for Processing Data and Computer System
patent-application, February 2016


Complexity-effective multicore coherence
conference, January 2012


Method, Apparatus, and System for Transactional Speculation Control Instructions
patent-application, January 2015


Message-driven processor in a concurrent computer
patent, May 1993


Multi-Core Computer Processor
patent-application, September 2014


Dynamic Detection and Correction of Incorrect Lock and Atomic Update Hint Bits
patent-application, March 2017


System and Method for Implementing Scalable Adaptive Reader-Writer Locks
patent-application, October 2015