DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Wafer-level handle replacement

Abstract

A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.

Inventors:
Issue Date:
Research Org.:
Ayar Labs, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE Advanced Research Projects Agency - Energy (ARPA-E)
OSTI Identifier:
1840378
Patent Number(s):
11101617
Application Number:
16/513,661
Assignee:
Ayar Labs, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G02 - OPTICS G02B - OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
AR0000850
Resource Type:
Patent
Resource Relation:
Patent File Date: 07/16/2019
Country of Publication:
United States
Language:
English

Citation Formats

Meade, Roy Edward. Wafer-level handle replacement. United States: N. p., 2021. Web.
Meade, Roy Edward. Wafer-level handle replacement. United States.
Meade, Roy Edward. Tue . "Wafer-level handle replacement". United States. https://www.osti.gov/servlets/purl/1840378.
@article{osti_1840378,
title = {Wafer-level handle replacement},
author = {Meade, Roy Edward},
abstractNote = {A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {8}
}

Works referenced in this record:

Wafer alignment marks protected by photoresist
patent-application, August 2001


Reduction of Substrate Optical Leakage in Integrated Photonic Circuits Through Localized Substrate Removal
patent-application, November 2009


Micro-optic fabrication using one-level gray-tone lithography
conference, April 1997


Alternate side lithographic substrate imaging
patent-application, July 2004


High contrast alignment marker for integrated circuit fabrication
patent, February 1983


Nanophotonic integration in state-of-the-art CMOS foundries
journal, January 2011


Multi-Run Selective Pattern and Etch Wafer Process
patent-application, December 2004


Wafer-Level Etching Methods for Planar Photonics Circuits and Devices
patent-application, January 2018


Method for making an optical waveguide assembly with integral alignment features
patent-application, December 2005


Optical coupling structure
patent-application, November 2007


Method of Transferring Device Layer to Transfer Substrate and Highly Thermal Conductive Substrate
patent-application, February 2020


Ultralow-Power High-Performance Si Photonic Transmitter
conference, January 2010


Methods for forming backside alignment markers useable in semiconductor lithography
patent-application, October 2006


Vertical Integration of CMOS Electronics with Photonic Devices
patent-application, August 2013


Single-chip microprocessor that communicates directly using light
journal, December 2015


Optical coupling structure
patent, November 2008


Substrate Holder, Lithographic Apparatus, Device Manufacturing Method, and Method of Manufacturing a Substrate Holder
patent-application, December 2014


Unframed via interconnection with dielectric etch stop
patent, August 1988


Method for defining alignment marks in a semiconductor wafer
patent, June 2005


Semiconductor opto-electronic devices with wafer bonded gratings
patent-application, January 2004