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Title: Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Abstract

A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1840359
Patent Number(s):
11093674
Application Number:
16/225,879
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
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DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/19/2018
Country of Publication:
United States
Language:
English

Citation Formats

Asaad, Sameh W., and Kapur, Mohit. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator. United States: N. p., 2021. Web.
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Asaad, Sameh W., & Kapur, Mohit. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator. United States.
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Asaad, Sameh W., and Kapur, Mohit. Tue . "Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator". United States. https://www.osti.gov/servlets/purl/1840359.
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@article{osti_1840359,
title = {Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator},
author = {Asaad, Sameh W. and Kapur, Mohit},
abstractNote = {A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Aug 17 00:00:00 EDT 2021},
month = {Tue Aug 17 00:00:00 EDT 2021}
}
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