DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Methods and apparatus to detect and annotate backedges in a dataflow graph

Abstract

Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.

Inventors:
; ; ;
Issue Date:
Research Org.:
Intel Corporation, Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1824057
Patent Number(s):
11029927
Application Number:
16/370,935
Assignee:
Intel Corporation (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B620873
Resource Type:
Patent
Resource Relation:
Patent File Date: 03/30/2019
Country of Publication:
United States
Language:
English

Citation Formats

ChoFleming, Jr., Kermin E., Tithi, Jesmin Jahan, Cranmer, Joshua, and Srinivasan, Suresh. Methods and apparatus to detect and annotate backedges in a dataflow graph. United States: N. p., 2021. Web.
ChoFleming, Jr., Kermin E., Tithi, Jesmin Jahan, Cranmer, Joshua, & Srinivasan, Suresh. Methods and apparatus to detect and annotate backedges in a dataflow graph. United States.
ChoFleming, Jr., Kermin E., Tithi, Jesmin Jahan, Cranmer, Joshua, and Srinivasan, Suresh. Tue . "Methods and apparatus to detect and annotate backedges in a dataflow graph". United States. https://www.osti.gov/servlets/purl/1824057.
@article{osti_1824057,
title = {Methods and apparatus to detect and annotate backedges in a dataflow graph},
author = {ChoFleming, Jr., Kermin E. and Tithi, Jesmin Jahan and Cranmer, Joshua and Srinivasan, Suresh},
abstractNote = {Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {6}
}

Works referenced in this record:

Data Distribution Fabric in Scalable GPU's
patent-application, December 2015


Multi-slice network processor
patent, February 2009


Data processing method and device
patent, April 2012


Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures
journal, September 2015


Soft connections
conference, January 2009


System and method for changing abilities of a process
patent, December 2015


Shared bypass bus structure
patent-application, August 2003


Branch-aware FIFO for interprocessor data sharing
patent, August 2007


Operator graph changes in response to dynamic connections in stream computing applications
patent, September 2015


Data Processing System, Apparatus and Method for Performing Fractional Multiply Operations
patent-application, December 2009


Network-on-Chip Dataflow Architecture
patent-application, November 2007


Path-Sensitive Dataflow Analysis Including Path Refinement
patent-application, June 2011


Processors, methods, and systems with a configurable spatial accelerator
patent, February 2020


System and Method of Load-Store Forwarding
patent-application, February 2009


Distributed Processing Architecture With Scalable Processing Layers
patent-application, December 2009


Apparatus, Methods, and Systems with a Configurable Spatial Accelerator
patent-application, July 2019


Method and apparatus for efficient scalable storage management
patent, February 2007


Distributed data set encryption and decryption
patent, April 2018


Dynamically Specialized Datapaths for energy efficient computing
conference, February 2011


Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices
journal, June 2019


Apparatus, Methods, and Systems for Unstructured Data Flow in a Configurable Spatial Accelerator
patent-application, October 2019


Handling cache misses by selectively flushing the pipeline
patent, March 2009


Apparatus, Methods, and Systems for Integrated Performance Monitoring in a Configurable Spatial Accelerator
patent-application, October 2019


Runtime Reconfigurable Dataflow Processor
patent-application, November 2012


Hardware Accelerator Architecture and Template for Web-Scale K-Means Clustering
patent-application, July 2018


Parallel Data Processing Apparatus
patent-application, September 2007


Dynamic Data Partitioning For Optimal Resource Utilization In A Parallel Data Processing System
patent-application, November 2012


Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
conference, January 2011


Resource access system and method
patent, September 2017


A preliminary architecture for a basic data-flow processor
conference, January 1975


Unidirectional bus architecture for SoC applications
patent-application, February 2004


Configurable processor system
patent, April 2004


Flash-Memory Device with RAID-type Controller
patent-application, November 2012


Distributed storage management platform architecture
patent-application, August 2002


Data Conversion Apparatus, Data Conversion Method, and Computer-Readable Recording Medium Storing Program
patent-application, January 2010


Instruction Set Architecture and Software Support for Register State Migration
patent-application, April 2018


System and method for zone access control
patent, March 2018


Semiconductor Integrated Circuit and Method for Operating Same
patent-application, January 2014


Ultra low power multiplier
patent, July 1998


Signal distribution device for load sharing multiprocessor
patent-application, December 2003


An Empirical Study of Iterative Data-Flow Analysis
conference, November 2006


Partitioned shared cache
patent-application, June 2007


Reconfigurable integrated circuit device
patent-application, February 2007


Deterministic Parallel Processing
journal, August 2006


Streaming Bridge Design with Host Interfaces and Network on Chip (NoC0Layers
patent-application, July 2015


Speed and area tradeoffs in cluster-based FPGA architectures
journal, February 2000


Automatic generation of hardware/software interfaces
conference, January 2012

  • King, Myron; Dave, Nirav
  • Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '12
  • https://doi.org/10.1145/2150976.2151011

Full access to memory interfaces via remote request
patent, October 2007


Technique for Scaling the Bandwidth of a Processing Element to Match the Bandwidth of an Interconnect
patent-application, March 2015


Processors, Methods, and Systems with a Configurable Spatial Accelerator
patent-application, January 2019


Methods and systems for saving draft electronic communications
patent, August 2015


Dataflow Predication
conference, December 2006


Multiprocessor System and Synchronous Engine Device Thereof
patent-application, June 2013


Tightly Coupled Processor Arrays Using Coarse Grained Reconfigurable Architecture with Iteration Level Commits
patent-application, May 2017


Low power array multiplier
patent, June 2009


Apparatus and Method for Selectable Hardware Accelerators i a Data Driven Architecture
patent-application, December 2019


Methods and Apparatus to Compile Code to Generate Data Flow Code
patent-application, February 2019


Intelligent Wide Port Phy Usage
patent-application, September 2017


Instruction Length Based Cracking for Instruction of Variable length Storage Operands
patent-application, August 2011


Apparatus, Methods, and Systems for Conditional Queues in a Configurable Spatial Accelerator
patent-application, October 2019


Apparatus and Method for Configuring Hardware to Operate in Multiple Modes During Runtime
patent-application, March 2018


Highly Scalable Architecture for Application Network Appliances
patent-application, March 2009


System and Method for Reducing Reconfiguration Power Usage
patent-application, January 2013


Safe Double Buffering Using DMA Safe Linked Lists
patent-application, December 2018


S-adenosyl methionine regulation of metabolic pathways and its use in diagnosis and therapy
patent, February 2000


Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port file
patent, November 2013


Content addressable memory architecture
patent-application, January 2007


Method and System for Referral Tracking
patent-application, December 2012


Processors, Methods, and Systems for a Configurable Spatial Accelerator with Transactional and Replay Features
patent-application, January 2019


Sequence Optimizations in a High-Performance Computing Environment
patent-application, February 2019


Load/store unit for a processor, and applications thereof
patent-application, April 2008


Guarded commands, nondeterminacy and formal derivation of programs
journal, August 1975


Bit Remapping Mechanism to Enhance Lossy Compression in Floating-Point Applications
patent-application, August 2016


Apparatus, Methods, and Systems for Operations in a Configurable Spatial Accelerator
patent-application, February 2019


Hierarchical and distributed information processing architecture for a container security system
patent-application, May 2007


Towards closing the energy gap between HOG and CNN features for embedded vision
conference, May 2017


Hierarchical Reconfigurable Computer Architecture
patent-application, May 2011


Method and Apparatus for Segmented Sequential Storage
patent-application, April 2016


Revisiting sorting for GPGPU stream architectures
conference, January 2010


Building a wavecache
patent-application, August 2006


Airsync: Enabling Distributed Multiuser MIMO with Full Multiplexing Gain
patent-application, November 2013


System and method of constructing data packets in a packet switch
patent, October 2010


Method and system for reliable multicast
patent, May 2011


Store Address Prediction for Memory Disambiguation in a Processing Device
patent-application, March 2015


System and Method for Relay Node Flow Control in a Wireless Communications System
patent-application, December 2010


ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
book, January 2003


Block-based data striping to flash memory
patent, February 2010


Hierarchical Instruction Scheduler
patent-application, June 2008


Hardware Acceleration for a Compressed Computation Database
patent-application, April 2016


Configurable Logic Constructs in a Loop Buffer
patent-application, January 2015


Solid State Device with Allocated Flash Cache
patent-application, September 2012


Energy-Efficient and High Performance CGRA-based Multi-Core Architecture
journal, June 2014


Computer with Hybrid Von-Neumann/Dataflow Execution Architecture
patent-application, February 2017


Method of locating packet for resend from retry buffer
patent-application, March 2008


Concurrent processing element system, and method
patent-application, July 2009


Variable Precision Floating Point Multiply-Add Circuit
patent-application, July 2014


Specifying Components in Graph-Based Programs
patent-application, March 2016


Distributed Job Manager Recovery
patent-application, December 2008


Task Backpressure and Deletion in a Multi-Flow Network Processor Architecture
patent-application, May 2013


Processors, Methods, and Systems with a Configurable Spatial Accelerator
patent-application, July 2013


Tuning congestion control in IP multicast to mitigate the impact of blockage
patent-application, October 2010


Bounded Dataflow Networks and Latency-Insensitive circuits
conference, July 2009


Buffer-Aware Transmission Rate Control for Real Time Video Streaming System
patent-application, November 2013


Applying Dataflow Analysis to Detecting Software Vulnerability
conference, February 2008


Hybrid Block-Based Processor and Custom Function Blocks
patent-application, November 2017


Scalable architecture for IP block integration
patent, December 2017


What's in a region?
journal, March 1993


Apparatus, Methods, and Systems for Memory Consistency in a Configurable Spatial Accelerator
patent-application, July 2019


Data processing device and method
patent, August 2014


System and Method for Encryption Key Management in a Mixed Infrastructure Stream Processing Framework
patent-application, July 2009


Chimaera
conference, January 2000


Tile-Based Processor Architecture Model for High-Efficiency Embedded Homogeneous Multicore Platforms
patent-application, November 2012


Method for Allocating Addresses to Data Buffers in Distributed Buffer Chipset
patent-application, February 2013


Computing Device with Asynchronous Auxiliary Execution Unit
patent-application, March 2012


Systems and Methods for Providing Distributed Technology Independent Memory Controllers
patent-application, November 2007


Method and Apparatus for Nearest Potential Store Tagging
patent-application, September 2014


Reconfigurable computing
journal, June 2002


Apparatus, Methods, and Systems for Multicast in a Configurable Spatial Accelerator
patent-application, July 2019


Processors, Methods, and Systems with a Configurable Spatial Accelerator Having a Sequencer Dataflow Operator
patent-application, April 2019


Data-Driven Integrated Circuit Architecture
patent-application, May 2012


Memory Ordering in Acceleration Hardware
patent-application, July 2018


Scheduling processing threads
patent-application, July 2004


Method and Apparatus for Saving Power of a Processor Socket in a Multi-Socket Computer System
patent-application, March 2016


Content/service handling and delivery
patent-application, May 2005


Dynamic Reduction of Stream Backpressure
patent-application, March 2013


High Availability Memory System
patent-application, August 2010


Integrated circuit and related improvements
patent-application, July 2004


Common Memory Programming
patent-application, December 2011


Method and Apparatus for Performing Memory Space Reservation and Management
patent-application, October 2013


Memory Violation Prediction
patent-application, March 2018


Storage Apparatus and Load Distribution Method
patent-application, July 2012


Fast Recalibration Circuitry for Input/Output (IO) Compensation Finite State Machine Power-Down-Exit
patent-application, March 2015


Processors, Methods and Systems for Debugging a Configurable Spatial Accelerator
patent-application, March 2019


Reconfigurable Array Processor for Floating-Point Operations
patent-application, April 2009


Processors, Methods, and Systems for a Memory Fence in a Configurable Spatial Accelerator
patent-application, March 2019


Distributed Clock Gating with Centralized State Machine Control
patent-application, December 2019


Electronic Device and Method for Converting Source Code into Machine Code
patent-application, November 2015


Incorporating a Spatial Array into One or More Programmable Processor Cores
patent-application, April 2015


Array-type computer processor
patent-application, August 2005


Distributed Data Storage by Means of Authorization Token
patent-application, October 2017


Parallelization of PLC Programs for Operation in Multi-processor environments
patent-application, October 2012


Floating Point Addition
patent-application, June 2008


Finding All the Elementary Circuits of a Directed Graph
journal, March 1975


Execution unit with data dependent conditional write instructions
patent, January 2013


MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources
conference, January 1996


Data Processing Apparatus and Method for Controlling Use of an Issue Queue
patent-application, July 2014


Specifying Control and Data Connections in Graph-Based Programs
patent-application, March 2016


Method and apparatus for efficient code generation for modulo scheduled uncounted loops
patent-application, December 2003


Processors and Methods for Configurable Clock Gating in a Spatial Array
patent-application, April 2019


Fused Multiply-Add Apparatus and Method
patent-application, May 2012


Vector Mask Driven Clock Gating for Power Efficiency of a Processor
patent-application, August 2015


LegUp
journal, September 2013


Variable precision floating point multiply-add circuit
patent, August 2015


Apparatus Including Core and Clock Gating Circuit and Method of Operating Same
patent-application, March 2017


Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators
journal, January 2017


Data Processing System Having Integrated Pipelined Array Data Processor
patent-application, April 2015


Non-Volatile Memory Based Mass Storage Devices and Methods for writing Data Thereto
patent-application, March 2013


Method for Performing Block Management, and Associated Memory Device and Controller Thereof
patent-application, March 2012


Reconfigurable Processor Fabric Implementation Using Satisfiability Analysis
patent-application, October 2018


The Stratix™ 10 Highly Pipelined FPGA Architecture
conference, February 2016


Methods and Apparatus to Insert Buffers in a Dataflow Graph
patent-application, July 2019


Low Latency Massive Parallel Data Processing Device
patent-application, January 2012


Packet processor with wide register set architecture
patent-application, September 2006


Thread Communications
patent-application, January 2009


Memory ordering in acceleration hardware
patent, February 2020


Iteration Support in a Heterogeneous Dataflow Engine
patent-application, January 2015


Executing Distributed Memory Operations Using Processing Elements Connected by Distributed Channels
patent-application, October 2019


Cryopreservation of Adipose Tissue for the Isolation of Mesenchymal Stem Cells
patent-application, January 2011


DMA-Based Acceleration of Command Push Buffer Between Host and Target Devices
patent-application, December 2011


I/O Circuit and Data Transmission Control Method
patent-application, June 2017


DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
journal, September 2012


Event scheduling for multi-port xDSL transceivers
patent-application, February 2005


Processor and Memory Control Method
patent-application, May 2009


Multiplier power saving design
patent, August 2003


Virtual Configuration Systems and Methods
patent-application, October 2018


Detecting and reissuing of loop instructions in reorder structure
patent, May 2015


Computer Accelerator System with Improved Efficiency
patent-application, September 2015


EIE: Efficient Inference Engine on Compressed Deep Neural Network
conference, June 2016


Transport-triggering vs. operation-triggering
book, January 1994


Multipoint-to-multipoint echo processing in a network switch
patent, August 1999


Processor Communications
patent-application, April 2015


Scalable high performance 3D graphics
patent, May 2008


Integrated circuit device with programmable analog subsystem
patent, October 2016


Data processing device, method of executing a program and method of compiling
patent, September 2003


Memory Controllers, Memory Systems, Solid State Drives and Methods for Processing a Number of Commands
patent-application, October 2010


Flash-Memory Device with RAID-type Controller
patent-application, December 2011


Methods for Specifying Processor Architectures for Programmable Integrated Circuits
patent-application, December 2017


Method and apparatus for modeling dataflow systems and realization to hardware
patent-application, November 2002


3D Semiconductor Device
patent-application, December 2011


Apparatus, Methods, and Systems for Remote Memory Access in a Configurable Spatial Accelerator
patent-application, October 2019


LOC semiconductor assembled with room temperature adhesive
patent-application, July 2002


Processors and Methods for Pipelined Runtime Services in a Spatial Array
patent-application, January 2019


Neighbor Determination in Video Decoding
patent-application, April 2014


Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
patent-application, February 2006


Processors, Methods, and Systems for a Configurable Spatial Accelerator with Security Power Reduction, and Performance Features
patent-application, January 2019


Block Floating Point Compression of Signal Data
patent-application, April 2011


Leveraging latency-insensitivity to ease multiple FPGA design
conference, January 2012

  • Fleming, Kermin Elliott; Adler, Michael; Pellauer, Michael
  • Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12
  • https://doi.org/10.1145/2145694.2145725

Multi-Level Table Grouping
patent-application, November 2017


Automated Dependency analyzer for Heterogeneously Programmed Data Processing System
patent-application, November 2018


A 167-Processor Computational Platform in 65 nm CMOS
journal, April 2009


Variable-Cycle, Event-Driven Multi-Execution Flash Processor
patent-application, January 2011


Apparatus, Method, and System for Instantaneous Cache State Recovery form Speculative Abort Commit
patent-application, June 2012


Techniques to Enable Communication Between a Processor and Voltage Regulator
patent-application, March 2018


Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
conference, June 2016


Hardware for machine learning: Challenges and opportunities
conference, April 2017


System and method for removing retired entries from a command buffer using tag information
patent-application, October 2006


Complex Matrix Multiplication Operations with Data Pre-Conditioning in a High Performance Computing Architecture
patent-application, February 2011


Low Power Clock Gating Circuit
patent-application, March 2019


Storage apparatus and load distribution method
patent-application, July 2008


Theory of latency-insensitive design
journal, January 2001

  • Carloni, L. P.; McMillan, K. L.; Sangiovanni-Vincentelli, A. L.
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 9
  • https://doi.org/10.1109/43.945302

The WaveScalar architecture
journal, May 2007


Method and system for scheduling in an adaptable computing engine
patent-application, December 2002


Data flow machine
patent-application, May 2006


Programmable logic integrated circuit for digital algorithmic functions
patent-application, September 2008


Loop execution with predicate computing for dataflow machines
patent, July 2019


Persistent Memory Replication in RDMA-Capable Networks
patent-application, November 2018


Low power arbiters in interconnection routers
patent-application, April 2007


Delayed-start method for minimizing internal switch congestion
patent, March 2011


Loop Execution with Predicate Computing for Dataflow Machines
patent-application, December 2018


Array Type Processor and Data Processing System
patent-application, December 2009


Asim: a performance model framework
journal, January 2002


Content service aggregation system
patent-application, July 2003


Memory read/write reordering
patent-application, September 2003


Method and system for digital signal processing in an adaptive computing engine
patent-application, February 2003


Efficient Spatial Processing Element Control via Triggered Instructions
journal, May 2014


A method to estimate the energy consumption of deep neural networks
conference, October 2017


Dynamic reduction of stream backpressure
patent, March 2015


Specialized Memory Disambiguation Mechanisms for Different Memory Read Access Types
patent-application, March 2015


14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
conference, January 2016


Method and Apparatus for Implementing Digital Logic Circuitry
patent-application, May 2019


Method and apparatus for timing information flow in a distributed system
patent-application, June 2016


Cache usage for concurrent multiple streams
patent-application, February 2004


Runtime Address Disambiguation in Acceleration Hardware
patent-application, July 2013


Efficient Processing of Deep Neural Networks: A Tutorial and Survey
journal, December 2017


Dynamically Configurable Placement Engine
patent-application, June 2013


Dynamic Runtime Choosing of Processing Communication Methods
patent-application, March 2013


Scheduling of data migration
patent, March 2017


Electronic Apparatus and Control Method Thereof
patent-application, September 2017


Method for burning MAC address
patent, December 2009


Increasing buffer locality during multiple table access operations
patent, August 2011


High-performance hybrid processor with configurable execution units
patent-application, July 2005


Floating-point processor with reduced power requirements for selectable subprecision
patent-application, August 2007


Processors, Methods, and Systems for a Configurable Spatial Accelerator with Performance Correctness, and Power Reduction Features
patent-application, January 2019


Eyeriss: a spatial architecture for energy-efficient dataflow for convolutional neural networks
journal, October 2016


Accumulator shadow register systems and methods
patent-application, June 2005


Parallel processing using multi-core processor
patent, December 2013


Processors and Methods for Privileged Configuration in a Spatial Array
patent-application, April 2019


Runtime address disambiguation in acceleration hardware
patent, November 2019


Shared memory apparatus and method for multiprocessor systems
patent-application, February 2002


Dependent Instruction Suppression
patent-application, December 2014


Memory transaction having implicit ordering effects
patent, July 2017


Instruction length based cracking for instruction of variable length storage operands
patent, July 2013


Methods and apparatus for interfacing between a host processor and a coprocessor
patent-application, June 2008


Shared Resource Multi-Thread Processor Array
patent-application, April 2012


Low Energy Consumption Mantissa Multiplication for Floating Point Multiply-Add Operations
patent-application, April 2018


Automatically Mapping Program Functions to Distributed Heterogeneous Platforms Based on Hardware Attributes and Specified Constraints
patent-application, October 2017


Apparatus and Method for Transmitting and Receiving Multimedia Data by Using NFC
patent-application, August 2018


Processors and Methods with Configurable Network-Based Operator Circuits
patent-application, January 2019


Maximal flow scheduling for a stream processing system
patent-application, December 2007


Symbolic Analyses of Dataflow Graphs
journal, March 2017

  • Bouakaz, Adnan; Fradet, Pascal; Girault, Alain
  • ACM Transactions on Design Automation of Electronic Systems, Vol. 22, Issue 2
  • https://doi.org/10.1145/3007898

Modifying Commands
patent-application, July 2010


Embedded System Performance
patent-application, March 2013


Designing Energy-Efficient Convolutional Neural Networks Using Energy-Aware Pruning
conference, July 2017


Distributed Memory Operations
patent-application, March 2015


Memory Controllers, Memory Systems, Solid State Devices and Methods for Processing a Number of Commands
patent-application, December 2012


Cache memory allocation method
patent, February 2006


Scaling to the end of silicon with EDGE architectures
journal, July 2004


A Characterization of Processor Performance in the vax-11/780
conference, January 1984


Execution of Data-Parallel Programs on Coarse-Grained Reconfigurable Architecture Hardware
patent-application, September 2015


Processor architecture
patent-application, April 2005


Data Processing Architectures for Packet Handling
patent-application, April 2011


Processors, Methods, and Systems with a Configurable Spatial Accelerator
patent-application, July 2018


Event System And Methods For Using Same
patent-application, January 2013


Fast Pattern Matching in Strings
journal, June 1977


Clocked ports
patent-application, October 2008


Configure Storage Class Memory Command
patent-application, December 2012


Optimizing Partial Reconfiguration of Multi-context Architectures
conference, December 2008


Method and apparatus for vector execution on a scalar machine
patent, January 2015


Secure migratable architecture having high availability
patent, September 2017