Three dimensional vertically structured electronic devices
Abstract
In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1824032
- Patent Number(s):
- 11024734
- Application Number:
- 15/398,652
- Assignee:
- Lawrence Livermore National Security, LLC (Livermore, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 01/04/2017
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, and Voss, Lars. Three dimensional vertically structured electronic devices. United States: N. p., 2021.
Web.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, & Voss, Lars. Three dimensional vertically structured electronic devices. United States.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, and Voss, Lars. Tue .
"Three dimensional vertically structured electronic devices". United States. https://www.osti.gov/servlets/purl/1824032.
@article{osti_1824032,
title = {Three dimensional vertically structured electronic devices},
author = {Conway, Adam and Harrison, Sara Elizabeth and Nikolic, Rebecca J. and Shao, Qinghui and Voss, Lars},
abstractNote = {In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {6}
}
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Works referenced in this record:
Semiconductor Device and Method for Manufacturing the Same
patent-application, January 2010
- Ohta, Hiroaki; Takasu, Hidemi
- US Patent Application 12/310366; 20100006894
Graded Heterojunction Nanowire Device
patent-application, May 2016
- Oxland, Richard Kenneth
- US Patent Application 14/554584; 20160149001
Nitride Semiconductor Device, Nitride Semiconductor Package, and Method for Manufacturing Nitride Semiconductor Device
patent-application, April 2010
- Otake, Hirotaka; Egami, Shin; Ohta, Hiroaki
- US Patent Application 12/524532; 20100078688
Method to planarize three-dimensional structures to enable conformal electrodes
patent, November 2012
- Nikolic, Rebecca J.; Conway, Adam; Graff, Robert T.
- US Patent Document 8,314,400
Three-dimensional boron particle loaded thermal neutron detector
patent-application, March 2013
- Nikolic, Rebecca J.; Conway, Adam M.; Graff, Robert T.
- US Patent Document 13/552307; 20130075848
Stress reduction for pillar filled structures
patent-application, July 2013
- Nikolic, Rebecca J.; Conway, Adam; Shao, Qinghui
- US Patent Document 13/742298; 20130187056
Method for manufacturing solid-state thermal neutron detectors with simultaneous high thermal neutron detection efficiency (>50%) and neutron to gamma discrimination (>1.0E4)
patent, October 2013
- Nikolic, Rebecca J.; Conway, Adam; Heineck, Daniel
- US Patent Document 8,558,188