Title: Instructions for performing multi-line memory accesses

Abstract

A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.

Inventors:

Roberts, David A.; Cho, Shenghsun

Issue Date:

2021-06-01

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1824028

Patent Number(s):

11023410

Application Number:

16/127,607

Assignee:

Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F12/0862 - with prefetch
G06F13/1673 - {using buffers}
G06F13/4027 - {using bus bridges
G06F15/17331 - {Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]}
G06F2212/1021 - Hit rate improvement
G06F2212/1024 - Latency reduction
G06F2212/6026 - Prefetching based on access pattern detection, e.g. stride based prefetch
G06F2212/6028 - Prefetching based on hints or prefetch instructions
G06F9/30043 - {LOAD or STORE instructions
G06F9/3455 - {using stride}

Show less

DOE Contract Number:  

AC52-07NA27344; B620717

Resource Type:

Patent

Resource Relation:

Patent File Date: 09/11/2018

Country of Publication:

United States

Language:

English