Instructions for performing multi-line memory accesses

Roberts, David A.; Cho, Shenghsun

Title: Instructions for performing multi-line memory accesses

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Abstract

A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.

Inventors:: Roberts, David A.; Cho, Shenghsun

Issue Date:: 2021-06-01

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1824028

Patent Number(s):: 11023410

Application Number:: 16/127,607

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/11/2018

Country of Publication:: United States

Language:: English

Citation Formats


                    Roberts, David A., and Cho, Shenghsun. Instructions for performing multi-line memory accesses.  United States: N. p., 2021. 
        Web.

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                    Roberts, David A., & Cho, Shenghsun. Instructions for performing multi-line memory accesses.  United States.

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                    Roberts, David A., and Cho, Shenghsun. Tue .  
        "Instructions for performing multi-line memory accesses".  United States.  https://www.osti.gov/servlets/purl/1824028.

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@article{osti_1824028,

  title        = {Instructions for performing multi-line memory accesses},

  author       = {Roberts, David A. and Cho, Shenghsun},

  abstractNote = {A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2021},

  month        = {6}

}

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