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Title: Synchronization between processes in a coordination namespace

Abstract

A system and method of supporting point-to-point synchronization among processes/nodes implementing different hardware barriers in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing data, communications, and coordination within applications and workflows implementing barriers in a multi-tier, multi-nodal tree hierarchy. The system provides a hardware accelerated mechanism to support barriers between the participating processes. Also architected is a tree structure for a barrier processing method where processes are mapped to nodes of a tree, e.g., a tree of degree k to provide an efficient way of scaling the number of processes in a tuple space/coordination namespace.

Inventors:
; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1824027
Patent Number(s):
11023291
Application Number:
16/409,377
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B621073
Resource Type:
Patent
Resource Relation:
Patent File Date: 05/10/2019
Country of Publication:
United States
Language:
English

Citation Formats

Jacob, Philip, Strenski, Philip N., and Johns, Charles. Synchronization between processes in a coordination namespace. United States: N. p., 2021. Web.
Jacob, Philip, Strenski, Philip N., & Johns, Charles. Synchronization between processes in a coordination namespace. United States.
Jacob, Philip, Strenski, Philip N., and Johns, Charles. Tue . "Synchronization between processes in a coordination namespace". United States. https://www.osti.gov/servlets/purl/1824027.
@article{osti_1824027,
title = {Synchronization between processes in a coordination namespace},
author = {Jacob, Philip and Strenski, Philip N. and Johns, Charles},
abstractNote = {A system and method of supporting point-to-point synchronization among processes/nodes implementing different hardware barriers in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing data, communications, and coordination within applications and workflows implementing barriers in a multi-tier, multi-nodal tree hierarchy. The system provides a hardware accelerated mechanism to support barriers between the participating processes. Also architected is a tree structure for a barrier processing method where processes are mapped to nodes of a tree, e.g., a tree of degree k to provide an efficient way of scaling the number of processes in a tuple space/coordination namespace.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {6}
}

Works referenced in this record:

Barriers and Synchronization for Machine Learning at Autonomous Machines
patent-application, October 2018


Technologies for Fast Synchronization Barriers for Many-Core Processing
patent-application, June 2016


Aggregation protocol
patent-application, March 2017


Hardware synchronization for embedded multi-core processors
conference, May 2011


Hardware Synchronization Barrier Between Processing Units
patent-application, November 2015