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Title: Method and apparatus for asynchronous scheduling

Abstract

A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.

Inventors:
; ;
Issue Date:
Research Org.:
Advanced Micro Devices, Inc., Sunnyvale, CA (United States); ATI Technologies ULC, Markham, CA (United States); Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1824026
Patent Number(s):
11023242
Application Number:
15/417,555
Assignee:
ATI Technologies UL (Markham, CA); Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B609201
Resource Type:
Patent
Resource Relation:
Patent File Date: 01/27/2017
Country of Publication:
United States
Language:
English

Citation Formats

Kalamatianos, John, Sadowski, Greg, and Gilani, Syed Zohaib M. Method and apparatus for asynchronous scheduling. United States: N. p., 2021. Web.
Kalamatianos, John, Sadowski, Greg, & Gilani, Syed Zohaib M. Method and apparatus for asynchronous scheduling. United States.
Kalamatianos, John, Sadowski, Greg, and Gilani, Syed Zohaib M. Tue . "Method and apparatus for asynchronous scheduling". United States. https://www.osti.gov/servlets/purl/1824026.
@article{osti_1824026,
title = {Method and apparatus for asynchronous scheduling},
author = {Kalamatianos, John and Sadowski, Greg and Gilani, Syed Zohaib M.},
abstractNote = {A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {6}
}

Works referenced in this record:

Data Processing Apparatus and Method for Controlling Use of an Issue Queue
patent-application, July 2014


Data Processor and Method of Lane Realignment
patent-application, April 2015


Method and apparatus for selecting the oldest queued instructions without data dependencies
patent, April 1998


Computing Device with Asynchronous Auxiliary Execution Unit
patent-application, March 2012