Three dimensional vertically structured electronic devices
Abstract
According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1823999
- Patent Number(s):
- 11018253
- Application Number:
- 14/990,612
- Assignee:
- Lawrence Livermore National Security, LLC (Livermore, CA)
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 01/07/2016
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, and Voss, Lars. Three dimensional vertically structured electronic devices. United States: N. p., 2021.
Web.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, & Voss, Lars. Three dimensional vertically structured electronic devices. United States.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, and Voss, Lars. Tue .
"Three dimensional vertically structured electronic devices". United States. https://www.osti.gov/servlets/purl/1823999.
@article{osti_1823999,
title = {Three dimensional vertically structured electronic devices},
author = {Conway, Adam and Harrison, Sara Elizabeth and Nikolic, Rebecca J. and Shao, Qinghui and Voss, Lars},
abstractNote = {According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {5}
}
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