Implementing a micro-operation cache with compaction

Kotra, Jagadish B.; Kalamatianos, John

Title: Implementing a micro-operation cache with compaction

Full Record
Other Related Research

Abstract

Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.

Inventors:: Kotra, Jagadish B.; Kalamatianos, John

Issue Date:: 2021-05-25

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1823995

Patent Number(s):: 11016763

Application Number:: 16/297,358

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 03/08/2019

Country of Publication:: United States

Language:: English

Citation Formats


                    Kotra, Jagadish B., and Kalamatianos, John. Implementing a micro-operation cache with compaction.  United States: N. p., 2021. 
        Web.

Copy to clipboard


                    Kotra, Jagadish B., & Kalamatianos, John. Implementing a micro-operation cache with compaction.  United States.

Copy to clipboard


                    Kotra, Jagadish B., and Kalamatianos, John. Tue .  
        "Implementing a micro-operation cache with compaction".  United States.  https://www.osti.gov/servlets/purl/1823995.

Copy to clipboard


                    
@article{osti_1823995,

  title        = {Implementing a micro-operation cache with compaction},

  author       = {Kotra, Jagadish B. and Kalamatianos, John},

  abstractNote = {Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2021},

  month        = {5}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Similar Records in DOE Patents and OSTI.GOV collections:

Method and apparatus for virtualizing the micro-op cache

Patent Kalamatianos, John; Kotra, Jagadish B.

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from havingmore » « less
Full Text Available
NIC atomic operation unit with caching and bandwidth mitigation

Patent Hemmert, Karl Scott; Underwood, Keith D.; Levenhagen, Michael J.

A network interface controller atomic operation unit and a network interface control method comprising, in an atomic operation unit of a network interface controller, using a write-through cache and employing a rate-limiting functional unit.
Full Text Available
Store operations to maintain cache coherence

Patent Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
Full Text Available
Store operations to maintain cache coherence

Patent Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
Full Text Available
Compact micro-concentrator for photovoltaic cells

Patent Terao, Akira; Krippendorf, Ralph

A reflector array comprises a plurality of partial parabolic reflectors arranged in rows and columns with each reflector directing radiation to a receiver or from a transmitter located at the focus of the reflector. In a compact photovoltaic cell arrangement, each cell is shielded from direct radiation by the adjacent reflector. The reflectors can be formed as one unit with reflective material or with the reflecting surfaces coated with aluminum, silver, or other suitable reflecting material. A secondary reflector can be positioned at the focus of a reflector for directing radiation to a receiver or from a transmitter located atmore » « less
Full Text Available

Similar Records