Interconnect architecture for three-dimensional processing systems
Abstract
A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1823880
- Patent Number(s):
- 10984838
- Application Number:
- 14/944,099
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- DOE Contract Number:
- AC52-07NA27344; B609201
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 11/17/2015
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Jayasena, Nuwan S., and Eckert, Yasuko. Interconnect architecture for three-dimensional processing systems. United States: N. p., 2021.
Web.
Jayasena, Nuwan S., & Eckert, Yasuko. Interconnect architecture for three-dimensional processing systems. United States.
Jayasena, Nuwan S., and Eckert, Yasuko. Tue .
"Interconnect architecture for three-dimensional processing systems". United States. https://www.osti.gov/servlets/purl/1823880.
@article{osti_1823880,
title = {Interconnect architecture for three-dimensional processing systems},
author = {Jayasena, Nuwan S. and Eckert, Yasuko},
abstractNote = {A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {4}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.