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Title: Shareable FPGA compute engine

Abstract

Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1823816
Patent Number(s):
10970118
Application Number:
15/974,014
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 05/08/2018
Country of Publication:
United States
Language:
English

Citation Formats

Kegel, Andrew G., and Roberts, David A.. Shareable FPGA compute engine. United States: N. p., 2021. Web.
Kegel, Andrew G., & Roberts, David A.. Shareable FPGA compute engine. United States.
Kegel, Andrew G., and Roberts, David A.. Tue . "Shareable FPGA compute engine". United States. https://www.osti.gov/servlets/purl/1823816.
@article{osti_1823816,
title = {Shareable FPGA compute engine},
author = {Kegel, Andrew G. and Roberts, David A.},
abstractNote = {Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {4}
}

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