Hardware accelerated dynamic work creation on a graphics processing unit
Abstract
A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1805681
- Patent Number(s):
- 10963299
- Application Number:
- 16/134,695
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 09/18/2018
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Gutierrez, Anthony, and Puthoor, Sooraj. Hardware accelerated dynamic work creation on a graphics processing unit. United States: N. p., 2021.
Web.
Gutierrez, Anthony, & Puthoor, Sooraj. Hardware accelerated dynamic work creation on a graphics processing unit. United States.
Gutierrez, Anthony, and Puthoor, Sooraj. Tue .
"Hardware accelerated dynamic work creation on a graphics processing unit". United States. https://www.osti.gov/servlets/purl/1805681.
@article{osti_1805681,
title = {Hardware accelerated dynamic work creation on a graphics processing unit},
author = {Gutierrez, Anthony and Puthoor, Sooraj},
abstractNote = {A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {3}
}
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Works referenced in this record:
Data Processing System and Method for Task Scheduling in a Data Processing System
patent-application, July 2014
- Beer-gingold, Shlomo; Weingarten, Eran; Zarubinsky, Michael
- US Patent Application 14/241926; 20140204103
Method and System of a Hierchical Task Scheduler for a Multi-thread System
patent-application, August 2016
- Kipp, Timothy James
- US Patent Application 15/011127; 20160239346
System and Method For Swarm Intelligence Using Dynamically Configurable Proactive Autonomous Agents Cells
patent-application, October 2018
- Iniguez, Alfonso
- US Patent Application 15/852480; 20180293096
Facilitating Dynamic Parallel Scheduling of Command Packets at Graphics Processing Units on Computing Devices
patent-application, August 2017
- Mrozek, Michael Andrzej
- US Patent Application 15/503201; 20170236246
Adaptive Scheduling for Task Assignment among Heterogenous Processor Cores
patent-application, February 2016
- Barik, Rajkishore; Shpeisman, Tatiana; Lewis, Brain T.
- US Patent Application 14/583247; 20160055612
Heterogenous Enqueuing and Dequeuing Mechanism for Task Scheduling
patent-application, December 2016
- Sander, Benjamin Thomas; Houston, Michael; Cheung, Newton
- US Patent Application 15/250385; 20160371116
Robust, Efficient Multiprocessor-coprocessor Interface
patent-application, February 2020
- Babich, Ronald; Burgess, John; Choquette, Jack
- US Patent Application 16/101247; 20200050451